plasmo wrote:
For hardware pan to work, the image memory need to be bigger than the display so the starting address of the horizontal/vertical define the region of memory to be displayed. Changing the starting addresses pan the display over the memory. Returning to your design where image memory is smaller than the display where you actually need to blank out the unused portion of the display. I see you are using H512 for horizontal blanking and V256 for vertical blank, so the active region is located at upper left corner of the display. You may want to move the active region to the center of the display and one way of doing that is load the counter with negative value and blank the display; when it rolls over, the screen becomes active in the center of the display. You can do this both horizontally and vertically since you have loadable counters.
Bill
Bill, you're a genius. Seriously. And thank you.
I went out and walked a couple miles thinking this through. Here is what I can say:
Right now I'm trying to accommodate for either the '161 or the '163, interchangeable. I would simply use solder jumpers to change the exact sync values by a little bit.
If I were to pan, say (640 - 2 x 256) / 2 = 64 pixels horizontally, then my sync signals and "reset" signal will also need to be shifted by 64 pixels. But it's no longer a reset signal, it's a load signal, which is synchronous in BOTH the '161 and '163. Thus my idea of having the async counter as an option/backup is no longer possible. The only way to allow for either is to be able to set my preload value to either 0 or 64, and likewise be able to change my horizontal sync signals between 656/592, 752/688, and 800/736. Likewise, I will need to be able to adjust the 800 to 799, and the 736 to 735, etc. Because my '688 chips are only 8-bits wide, I would somehow have to have my counter values for 1,2,4,8,16,32, and 64 available to be changed, leaving me with only one bit for anything higher/lower, which would definitely require more logic gates, which only decreases my available time between clock cycles.
This argument extends to the vertical timing as well.
In a way, I'm saying having the option to use the '161 OR the '163 would no longer work (well it would work, but the because I wouldn't be using the reset there would be no difference between the two chips). My ability to try the async OR the sync counter idea would be off the table.
So here's my thoughts: I will keep this particular board design, without pan. And I will also make a second design that is ONLY synchronous but panned horizontally and vertically by 64 pixels, that's center screen horizontally and kinda sorta center vertically. In that second design I won't need the flip-flop as a clock divider, so I can use that as the second SR Latch, gaining me two NAND gates to help with my enable signals (might need to do some solder jumpers on my main board now too).
I wouldn't want to call this "feature creep", but it would be a non-essential. Still, that is such an excellent idea! And if I'm going to have 2 boards printed, what does it matter if I make a third board, it will only be $8 more on JLCPCB.
Thank you again Bill, I'll keep you updated.
Chad