Attempt at '816

[akohlbecker]

and3rson wrote:

In the datasheet, on the page with address demux curcuit, what does the square rotated by 45° mean? Is it some sort of buffer?

No idea, actually! Wouldn't make sense for it to be a buffer, though, since the buffer is the '245

[GARTHWILSON]

Someone here theorized years ago that it's two arrows, back to back, meaning data flows in both directions.

[BigDumbDinosaur]

akohlbecker wrote:

and3rson wrote:

In the datasheet, on the page with address demux curcuit, what does the square rotated by 45° mean?  Is it some sort of buffer?

No idea, actually!  Wouldn't sense for it to be a buffer, though, since the buffer is the '245.

Way back in the day when I was first studying “modern” digital electronics (c. 1969—before that, it was mostly tubes I worked with), that symbol was used to signify a bi-directional bus.  Along with the “diamond,” there would be a symbol indicating how many distinct circuits were in the bus.  You can see both of those elements in the 65C816 data sheet on the page illustrating the A16-A23 capture logic.

Symbols such as that evolved because schematics in those days were manually drawn, and there were sometimes a LOT of ICs in a large system, many interconnected via buses.  The ZIP Mail Translator (ZMT) I worked on in 1970 had over 300 ICs, most of them basic gates.  As I recall, the ZMT had three main buses for passing data, addresses and control signals.  The schematic for the thing went page after page after page after...more pages.  So a lot of symbols were used to reduce the required amount of drafting labor.  The diamond-shaped bus symbol was one such symbol, along with a somewhat-triangular zoogie that represented a uni-directional bus.

Speaking of bank capture circuits, here’s an interesting version.

65c816_bank_latch.pdf

65C816 Bank Capture

(267.87 KiB) Downloaded 218 times

[BigDumbDinosaur]

and3rson wrote:

Are there any benefits of using a GAL instead of a 74xx latch?

It depends.  The GAL would be more consistent, timing-wise, but potentially slower than, say, a 74AHC573.  Given the timing window associated with latching A16-A23, I’d say the GAL would be more advantageous in a system that is expected to run at the high end of the 65C816’s capabilities, mostly because its worst-case performance is very predictable (assuming you don’t use pin nodes in your logic).

The main negative with using any PLD is its outputs are TTL, not CMOS.  A TTL device’s maximum VOH is theoretically 3.4 volts, which is slightly shy of an “official” CMOS logic 1.  That means you would be working with lower noise margins than you would with all-CMOS glue logic.  You can mitigate this to some extent by using a four-layer PCB with inner ground and power planes, and lots of bypassing.  While that obviously won’t affect voltage levels, it will reduce the overall noise level, as well as reduce the risk of ground bounce, the latter which is potentially more “deadly” than noise.

Something else to consider is GALs tend to be power hogs.

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Edit: Fixed typo.

[GARTHWILSON]

BigDumbDinosaur wrote:

The schematic for the thing went page after page after page after...more pages.

A bit OT, but I'll bite.  How big were the pages?  It's sure easier when it all fits on one big page and you don't have to look for tags or have to put the pages side by side and one above the other.  Back then, they probably just had blueprints, right?  And blueprint machines didn't let you draw as small as the later photocopies which you could get in 48" or 60" wide and as long as the roll of paper.  I stopped at C size (17"x22" or 18"x24") in my work; but by then, we could get big photocopies and I could draw pretty small and get many hundreds of components on one page.  The last time I tried to get a copy though, the place I had used was out of business since everything is CAD now, so I went to Kinko's, and they nearly destroyed my big drawing that took days to draw.  The excuse he gave was to blame me for using non-standard paper!  He was too young to know about vellum which had been the standard paper for any kind of technical drawing for decades.  At the last place I worked, around 1990, we had a large HP plotter that could do, IIRC, E size (36"x48"), and used pencil lead which was nice because if, after a meeting with other engineers, you wanted to make a small change, you could use an eraser and pencil it in rather than having to draw the whole thing again which could take a long time depending on the complexity.  The pencil leads started out a few inches long, like what goes into a mechanical pencil, and it fed the lead as necessary, and sensed when it was time to automatically load a new lead.  The interface protocol was HPGL.

[drogon]

and3rson wrote:

drogon wrote:

Just to add another data-point:

In my ruby 816 system, I use a GAL to latch the upper N address bits and no separate data bus buffer. Works for me, but I only have one peripheral - a 65C22 and simple address decoding done in another GAL to allow for 512KB of RAM and the VIA.

-Gordon

Are there any benefits of using a GAL instead of a 74xx latch?

Maybe not, but for me, it does other stuff too. e.g. I also have BE going into it, so it pulls the upper address lines low when I pull BE low. It also manages the "wire-or" for IRQs and blocks IRQs when Rdy is low, and does address decoding for a 2nd 512KB RAM IC and generates a separate signal for the 2nd GAL to use as part of the address decoding for the VIA.

-Gordon

[akohlbecker]

Can you implement a transparent latch with a GAL? I thought they only had D flip flops and you had to upgrade to a CPLDs to do that

[BigDumbDinosaur]

GARTHWILSON wrote:

BigDumbDinosaur wrote:

The schematic for the thing went page after page after page after...more pages.

A bit OT, but I'll bite.  How big were the pages?

If memory serves me, I think the drawings were D-sized.  There were a lot of them, all neatly bound into a “book.”  This was the U.S. Post Office, after all.  Government entities are all about organization...or so they’d like us to think. 

[BigDumbDinosaur]

drogon wrote:

and3rson wrote:

drogon wrote:

Just to add another data-point:

In my ruby 816 system, I use a GAL to latch the upper N address bits and no separate data bus buffer. Works for me, but I only have one peripheral - a 65C22 and simple address decoding done in another GAL to allow for 512KB of RAM and the VIA.

-Gordon

Are there any benefits of using a GAL instead of a 74xx latch?

Maybe not, but for me, it does other stuff too. e.g. I also have BE going into it, so it pulls the upper address lines low when I pull BE low. It also manages the "wire-or" for IRQs and blocks IRQs when Rdy is low, and does address decoding for a 2nd 512KB RAM IC and generates a separate signal for the 2nd GAL to use as part of the address decoding for the VIA.

-Gordon

Have you ever published the code in your GALs?

[gfoot]

akohlbecker wrote:

Can you implement a transparent latch with a GAL? I thought they only had D flip flops and you had to upgrade to a CPLDs to do that

I think you can do things like D = D & PHI2 # Q & !PHI2 but I seem to remember having trouble with the cupl simulator if I took this too far. This is using combinatorial pins, not registered ones, as it's asynchronous.

[drogon]

BigDumbDinosaur wrote:

Have you ever published the code in your GALs?

No. I gave up on the open source thing after the open source "community" gave up on me.

I also use a tool that no-one else uses - GALasm, although it's a fairly trivial text file.

I sometimes publish things under a "source available" thing, but it's rare these days. Also the reality is that no-one else is going to build one of my boards so it's a bit moot.

Gordon

[Proxy]

eh, i'm not a fan of that mentality.

i made my 65816 SBC's schematics, CPLD logic, and BIOS ROM public. because having more resources and working examples online is always a good thing.
I don't expect anyone to ever actually build my SBC, and i'm perfectly ok with that.
but if someone is looking for some examples of how to make a 65816 SBC, they can use my design as a base or use it to look at how i did specific things like the latching circuit to then design their own.

that's why i would always recommend publishing details (schematics, code, etc) about larger projects (even if it has it's own thread where you can follow along the development), so that others might use it as learning resource in the future.
if you don't, then once you leave the community all your knowledge will be pretty much lost except for the few snippets thrown around in forum posts (which might be difficult to find).

that also applies for anything being sold, once you stop selling something there is no reason to not publish it, so others can make their own.
i still hate that about the kipper2k Amiga RAM expansion, which was a very simple design with some DRAM and a CPLD that plugs into the CPU socket to give an A500/600 4-8MB of RAM. but he stopped selling it without ever making the design public. the design was popular enough that it was remade from scratch and open sourced, but that extra work could've been easily avoided.

[and3rson]

drogon wrote:

I also use a tool that no-one else uses - GALasm, although it's a fairly trivial text file.

I use it, too - it's my favorite assember for GAL/ATF PLDs. I also find its source syntax easier to read than WinCUPL.

Proxy wrote:

I don't expect anyone to ever actually build my SBC, and i'm perfectly ok with that.
but if someone is looking for some examples of how to make a 65816 SBC, they can use my design as a base or use it to look at how i did specific things like the latching circuit to then design their own.

This. I'm often very happy to find someone's SBC with all the sources, since it really helps understand how the thing is supposed to work. I've learned a lot from other people's projects.
I think that's the true spirit of the Open Source, and I've always been trying to make all my works open - not for fame or commendations, but just in case it helps someone as much as similar projects used to help me.

EDIT: Sometimes, the most obscure projects with only few Github stars are the most valuable ones due to their rarity: I recently played with Intel 8008, and I found someone's SBC on Github. That was the only project with a great documentation, schematics and all the sources included, even PLD sources for GAL. Needless to say, it helped me tremendously to understand 8008's internals and usecases.

[BigEd]

(Just to say, I like to open source my own works, and I much prefer when published works have open source licenses, failing which I prefer published code to private code, but finally I also respect the decision of anyone who feels they need to do otherwise. Ideally we can still share our project stories and share ideas.)

[plasmo]

All my 70+ designs except two are sufficiently documented to be replicated by others. They are stored in retrobrewcomputers under plasmo. Ultimately the documentations are for myself because it is where I can find the most current designs snap shots. If you are interested in any of my designs but couldn’t find certain document, let me know and I’ll upload the missing document. The two exception are Ultrawarp and IOU for Apple IIe implemented in CPLD; I am working in a team on these projects and agreed not to release the design files.
Bill