Reading several recent posts about hardware implemented on solderless breadboard spurred me to think about an add-on board that may help the debugging of breadboard hardware. Assuming the breadboard contains a microprocessor in 600-mil DIP package such as 6502, Z80, 6809, etc, the basic idea is a board that stacks over the microprocessor to provides user interface. This board has 2 rows of pins 0.8" wide with pin functions match the target microprocessor. It plugs over the microprocessor and monitor/control the activities of the microprocessor with several modes of operations. This board contains two components, 128K RAM and CPLD, and 2 headers, serial port and JTAG port. Different processors will have different routed add-on board, but the concept is the same.

I'm thinking of 4 different modes of operations depending on how the CPLD is programmed:
1. Enhanced NOP test where a small ROM is programmed in CPLD to bootstrap the processor and perform simple test of the breadboard hardware.
2. Instruction tracing where every instruction executed is output on the serial port. This requires processor to run very slowly but serial port to transmit data at high data rate such as 460K.
3. Instruction logging where processor is running at full speed and data is saved in RAM.
4. Functioning computer where processor with RAM+CPLD forms a simple computer that can load and run program through serial port.

Mode 1 is easy to do because CPLD can be programmed with 64-128 bytes of ROM data; mode 2 was done for RC2014 Z80 where Z80 clock is 10KHz and address/data are send out serially at 460K. With hoglet's 6502 instruction decoder the CPU clock maybe 3 times higher; mode 3 hasn't been done (by me) so it is an unknown; mode 4 is basically CRC65 design but without compact disk interface.

Solderless breadboard have 5 rows of connections on each side so two rows at 0.8" spacing plugged over 0.6" DIP allow one row of solderless connections at one side and two rows of connections at the other side. The 0.8" wide footprint is sufficient to accommodate hand-wired SOJ RAM and PLCC44 CPLD. For PC board, the row spacing needs to be 0.9" to accommodate PLCC44 or 100-pin QFP.

To check out the concept, I have started building a prototype board mounting SOJ RAM and PLCC44 CPLD in "dead bug" fashion on perf board. The two rows of pins are 0.8" wide. The CPLD is pre-programmed with CRC65 equations and the schematic is based on CRC65.

I've layout the ground/VCC and connected up the clock and 8 data line. While I enjoy building hardware, this prototype effort is tedious and I can only do a dozen or so connections before the fun ran out. I'm stopping tonight to write down my work so far. To be continued.
Bill

Nice idea. Be aware that it can be quite awkward fitting all the wires in around a 0.6" part, especially for the buses which might go to multiple destinations. Only having one row of pins on one side will make that harder.

I see that the CPLD's size forces this width - but I wonder if it's possible to fit pin headers or sockets to the board to allow connecting wires that don't fit in any more? Or maybe a mezzanine board above it with extra breakout pins or sockets?

I love the basic direction of this idea and could sure use it right now! My solderless breadboard has gotten really crowded around the W65C02S PDIP. Anything that pushes out horizontally from the pins is a no-go. However, maybe stacking vertically from *under* the CPU PDIP with a custom shield-like board could fit, with a bundle of wires coming off that could route out the ends. Just thinking out loud...

_________________
--Mark

I completed the wiring of the diagnostic prototype. It is quite dense and tedious to wire. (I don't think I'll do wired prototype for Z80 version) There are several pull up resistors at the back for RDY, NMI, IRQ, SOB, etc. Powering it up by itself, the current consumption looks reasonable. I'm able to read/verify the pre-programmed CPLD.

On the solderless breadboard, I have 6502, oscillator, and voltage supervisor. I plug in the diagnostic prototype and powered up, no magic smoke escaped. My first attempt is mode 4 operation where 6502 with the diagnostic board should be able to load program through the serial port, but that was not successful. So I'll need to visually inspect all connections. If it passes visual inspection but still not able to run mode 4, I'll need to start with mode 1, writing simple ROM program in CPLD to test 6502 and RAM, another word, using the diagnostic prototype to diagnose itself.

Thanks for the comments, I'll address them in a separate post.
Bill
Edit, add the schematic of the diagnostic prototype board

If 44-pin TQFP CPLD is used instead of PLCC44, it is possible to put RAM and CPLD inside 0.6" footprint. The routing is complex and require 4 signal layers. It may be possible to put RAM and CPLD under 40-pin 6502. Samtec makes machined sockets with extra long tails, so 6502 can plug into the sockets then the stacked assembly of 6502+RAM+CPLD with long tails plug into the solderless breadboard.

Sounds like the vertical stacking is plausible then, nice. I've also been looking at those Samtec stacking headers. Looks like Sager has the best price, but I don't have experience buying from them. For SRAM I've got some 512kx8 10ns CY7C1049G-10VXI, which are in SOJ 36 packages that look like they would fit (0.44mm to the outer edge of the pins). I'm looking forward to see how far you get with this -- it will really help with debugging at full clock speed when single stepping is not realistic.

_________________
--Mark

It turns out there was nothing wrong with wiring of the diagnostic prototype; the problem is 6502's BE (pin 36) is not pulled up to VCC. So once BE is pulled up, the board booted and able to load program via serial port. Picture shows the 6502 monitor loaded and ran. It is running with 14.7MHz 6502 clock.
Bill

Since the diagnostic prototype + 6502 is small and compact, I thought it may overclock into 20+Mhz even though power/ground distribution is poor. It is easy to double the clock to 29.5MHz and run serial port at 230K without changing the CPLD design so that's what I tried. At 29.5MHz, it doesn't quite work at nominal 5V voltage, but when I cranked up the voltage to 5.4V, it will boot and pass memory diagnostic, most of the time. Here is a case where it failed memory diagnostic. Power consumption at 5.4V running memory diag is 150mA.

29.5MHz is clearly over the edge but the diagnostic board should work well at the nominal 14.7MHz.
Bill

Edit: I tried Klaus Dormann's 6502tst and 65C02_extended_opcodes_test at 29.5MHz. They both passed with several repetitions of the tests.

Exciting to see this in action! I'm also impressed at getting the PDIP up to almost 30 MHz, with solid detailed diagnostics.

What hardware/software environment do you use to program this MAX 7000 class CPLD? Do you recommend this series of CPLDs or is this just what you had around? I'm a total newby to CPLDs.

--Mark

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--Mark

CPLD (Complex programmable logic device) is 1990's technology designed to replace large number of TTL logic with one device with the added benefit of being programmable so the logic circuitry can be changed in software. EPM7XXXS parts are now obsolete but still can be acquired used. The development tool is Quartus, rev 13 or older; older Quartus can be downloaded for free. EPM7XXXS can be reprogrammed in-situ using USB blaster or clone. USB Blaster clone is inexpensive, about $10. Because it is designed to replace TTL logic, design entries are frequently done in schematic and Quartus has a large TTL library, so it is fairly easy to enter the original TTL logic schematic into Quartus. Quartus also support high level hardware language like Verilog or VHDL.

EPM7000S used to be cheaply available but now it is almost as expensive as its Atmel equivalent, ATF1504 is equivalent to EPM7064S and ATF1508 is equivalent to ATF1508. While Atmel ATF150x family is currently in production, its programmer is expensive ($60) and its development tools are downright primitive. Many people here are using WinCUPL which is so buggy I absolutely refuse to use it. ATF150x being equivalent to EPM7xxxS, it is possible to design in Quartus and use a translation tool to convert it to ATF150x format. Unfortunately, the conversion tool can be buggy as well.

My solution is stockpiling large supply of EPM7XXXS parts and design in Quartus so I don't have to worry about part availabilities or software translation bugs.
Bill
PS, 6502.org has a dedicated section on Programmable Logic. I have long thread in the Programmable Logic section about 6502+CPLD trainer. There are many design examples there.
viewtopic.php?f=10&t=6974

A quick update; this is 2-layer PC board version of the diagnostic prototype.. First photo shows the backside before plugging into the solderless breadboard; 2nd picture shows the diagnostic hat plugging over a W65C02. It works at the nominal 14.7Mhz. It also works at 29.5MHz @5V, room temperature. It may be interesting to see what is its top speed.

Updated schematic is attached.

I also made a pcb version of diagnostic hat for Z80.
Bill

This is looking very usable -- quick work! This is encouraging me to go vertical and learn CPLDs.

_________________
--Mark

While CPLD is very capable, I have sensed a common sentiment among the retro community that CPLD is not "retro enough" thus not widely adopted. 6502.org is one of the few retro forums with dedicated Programmable Logic section and even that contained mostly SPLD (simple programmable logic device) topics instead of CPLD. CPLD's adoption is also hampered by hard-to-find Altera parts or expensive ATF150x tools and associated buggy WinCUPL development tool. Then again, we are not here because it is easy, cheap, and readily available off-the-shelf.
Bill

For any given preference as to what's in and what's out, there'll always be a few people prepared to speak up. Follow your own preference, and don't mistake a vocal few for a consensus. (It can be worthwhile to start a project by outlining the chosen parameters, although it doesn't always forestall contrary views.)

So, if you like CPLDs, in a given week, and if you can find them and program them, go for it! If in another week you prefer through-hole 74 series, do that instead. And the week after, try FPGAs...

Perhaps cost and availability are the bigger design consideration. I certainly have seen plethora of retro computers with cheap and readily available modern microcontrollers as the I/O processor.
Bill