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PostPosted: Fri Jul 14, 2023 9:31 am 
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Joined: Fri Jul 14, 2023 8:04 am
Posts: 1
Location: Czechia
Hi, I'm Ondra. I'm glad I found this forum. Here are a few things about me.

I have been interested in electronics, electricity, and tinkering since I was a child. It started with taking apart toys and figuring out how they worked. I played with a soldering iron, switches, and light bulbs. The first computer I had was a Didaktik M, a Czechoslovak clone of the ZX Spectrum. I programmed in BASIC. It was just child's play, but I enjoyed it.

Later, I continued with x86 in DOS. I programmed simple scripts in the shell. Then I got to the PIC16F84 processor. I programmed in assembler. It was really hard, but also very rewarding. Only here I really understood how a computer works.

Embedded systems still interest me and I am interested in them. But I feel that they are getting more complex. Yes, MicroPython is an amazing language, but assembler and simple hardware have their charm. Knowing exactly what it does.

More and more it draws me back to the roots. Now I am interested in the 62C02 processor. I build a KIM-1 clone based on Arduino. I enjoy working with low-level programming. I like systems like the keyboard input monitor, because I can program right away. It reminds me a lot of old Paradox security systems.


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PostPosted: Fri Jul 14, 2023 9:42 am 
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Joined: Thu May 28, 2009 9:46 pm
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eye3sg wrote:
I build a KIM-1 clone based on Arduino.

Welcome to 6502 land.

How did you build your clone? Do you have any photos you can show us? (Photos can be attached to posts here, as well as PDFs and ordinary text files.)

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x86?  We ain't got no x86.  We don't NEED no stinking x86!


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PostPosted: Thu Dec 28, 2023 8:29 am 
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Joined: Thu Dec 28, 2023 8:19 am
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Hi 6502 lovers,
I am an old hardware & software developer, just retired and now with a little time to try do develop some crazy ideas :D
Thank you for this space and for shared know how, 6502 was my first processor (I start with KIM1..) and I dont forget all adventures with this evergreen pioneer.
Hear you soon !
maurizio


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PostPosted: Thu Dec 28, 2023 3:19 pm 
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Joined: Fri Dec 11, 2009 3:50 pm
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Location: Ontario, Canada
Welcome, maurizio! I too am fond of crazy ideas :roll: :lol: and I look forward to hearing more about your activities in the past and going forward.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html


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PostPosted: Thu Dec 28, 2023 9:34 pm 
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Welcome.  Let's hear those "crazy ideas."  Crazy ideas are often DOA; but other times they're the kind that make me say, "That's ingenious!  So simple, and yet a perfect solution!  Why didn't I think of that?!"  Even now, closing in on 50 years after the introduction of the 6502, I expect there are still great techniques, especially in software, that remain to be thought of, or at least published.

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PostPosted: Fri Dec 29, 2023 9:12 am 
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GARTHWILSON wrote:
Welcome.  Let's hear those "crazy ideas."  Crazy ideas are often DOA; but other times they're the kind that make me say, "That's ingenious!  So simple, and yet a perfect solution!  Why didn't I think of that?!"  Even now, closing in on 50 years after the introduction of the 6502, I expect there are still great techniques, especially in software, that remain to be thought of, or at least published.


Hi Garth,

there are a huge quantity of 3D and very interesting articles in your website and in this forum, it's no easy for me to find specific argument.. but I will try in the next year :wink:
In the meantime pardon me if I ask infos about my first curiosity: sharing RAM with external device, to allow pseudo "transparent" use of one intelligent HMI.
In the past I solve this job with dual port RAM (see attachment) but hardware implementation is not cheap; I remember that old Commodore machines share part of system ram with video device (VIC 6561)
Well, in your opinion should be possible to manage system RAM during PHI2=0 when 65C02 dont access to RAM/ROM ?
For example, with one system board that run 65C02 at 1.8432 we will have:

- PHI2 active more or less for 270 nS and inactive for similar time
- PHI1 active for 270nS , alternate to PHI2
- we dont permit access bus for 50 nS from PHI rising to avoid overlap on systemn address/data bus

Teorically - with 70nS RAM - we have more than 100nS to read or write 1 byte of RAM (obviously non cuncurrent writing, unsemaphored and asinchronous data exchange require use of 2 separated memory block..)

I suppose that this opportunity was already discussed, do you have memory of that ?

Thank you in advance !

maurizio


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