sburrow wrote:
So what are you working on specifically? I see your "Glue" picture, but what is the goal here eventually?
I'm working on a full schematic for my next project. It will be a more full-featured "home computer" style build pulling together what I've learned so far from previous projects, and expanding a bit. (It will have some basic RAM/ROM banking, which I haven't done before, and an ACIA for serial connections.)
Here's today's KiCAD headscratcher. I wired up the CPU, RAM, and ROM like this:
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I created global labels A[0..15] and D[0..7] for the address and data buses, then unfolded the connections for each line where it connects to the various ICs, just like you see in the picture. When I run the error check, there's no complaints on this sheet. Over on the I/O sheet I wired up the VIAs like this:
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You can see I created the same data bus, then broke out its individual lines. I also broke out individual address lines to connect them to the VIAs' register select lines. Again, no problems. On that same page I also broke out D0 to create an output "register" to control RAM/ROM banking:
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That also worked OK! So the concept I'm working from is that creating a bus with the X[Na..Na+z] syntax creates all the individual labels (Na, Na+1, Na+2, etc.) and makes them available for individual connections. However, over on the glue logic sheet, where I did exactly the same thing for the address bus, I get a bunch of errors saying "label A4 is not connected to anything," "label A5 is not connected to anything," etc., for every address label that I fanned out from the address bus.
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I'm stumped!