Ideal glue logic family for 6502 interfacing?

[matthew180]

Are there any glue logic families that were designed to be used with the NMOS CPUs of the late 70s and early 80s, like the 6502? Most of the retro computers seem to be built with TTL 74LS logic, even when the CPUs migrated to CMOS later in early/mid 80s (65C02, etc.).

Tangentially I'm trying to help someone interface a modern LVC part with a 65C02, and it is not working out. Mixing logic families seems to be hit and miss, and guessing is getting tiring. Working out what will and will not talk to each other is an exercise in frustration in my experience.

When these CPUs were designed, I have to believe there were specific logic families they were intended to be used with?

Thanks!

[BigDumbDinosaur]

matthew180 wrote:

Tangentially I'm trying to help someone interface a modern LVC part with a 65C02, and it is not working out.

What do you mean by “it is not working out”? Who is the manufacturer of the 65C02? Are you sure it actually is a 65C02?

All of the common LVC-family gates produce CMOS-level outputs. There should be no compatibility issues with the 65C02. As for the NMOS 6502, it operates at TTL levels, which is why it was extensively used with 74LS logic. A CMOS device can successfully drive an NMOS 6502, but not the other way around, unless the CMOS device is of the 74xCT family.

There is plenty of info on line about logic family compatibility. A quick session in your favorite search engine should show the way.

[matthew180]

BigDumbDinosaur wrote:

What do you mean by “it is not working out”? Who is the manufacturer of the 65C02? Are you sure it actually is a 65C02?

wd65c02

That is all I know currently. However, since posting I may have figured out the problem. The 6502 has a very long (~300ns) delay from the time the R/!W goes low (for a write op) to when there is valid data on the data bus. That coupled with some assumptions I made, and I think this is causing the problem.

BigDumbDinosaur wrote:

There is plenty of info on line about logic family compatibility. A quick session in your favorite search engine should show the way.

I have been thrashing around the 'Net for a while, it is a hard topic to search, and I have yet to find a definitive answer (at least one that gives me confidence that I'm making the right choice, etc.)

BigDumbDinosaur wrote:

... As for the NMOS 6502, it operates at TTL levels, ...

This is the kind of info I'm looking for, so thanks!

Interestingly I have a lot of 80s era books for building your own computer, but they are all around the Z80, 8080, 8085, and 6809. Nothing in my library for the 6502, so I need to remedy that.

[Proxy]

Usually you validate the RWB output with the clock (by ANDing them together) since data is only valid while the clock is high but RWB can be valid way before that.
I doubt it's a fixed time of 300ns as well since that wouldn't make sense when running at +16MHz. So it depends on your clock speed.

Check the 6502 primer for more detail.
https://wilsonminesco.com/6502primer/

[Paganini]

matthew180 wrote:

I have been thrashing around the 'Net for a while, it is a hard topic to search, and I have yet to find a definitive answer (at least one that gives me confidence that I'm making the right choice, etc.)

Here are two discussions of this topic that I have found helpful:

https://wilsonminesco.com/6502primer/LogicFamilies.html (by our own Garth Wilson)

https://www.retrobrewcomputers.org/doku ... bstitution

I personally am fond of AHC. It's generally a good middle ground, being nearly as fast as AC, while nearly as forgiving as HC, which is important for me because I like to prototype things on breadboards before making more permanent versions. The glue logic for my "Peanutbutter-1" wire-wrapped SBC is an HC688 and an AHC139, and it runs at at least 12.6MHz.

[matthew180]

Proxy wrote:

Usually you validate the RWB output with the clock (by ANDing them together) since data is only valid while the clock is high but RWB can be valid way before that.
I doubt it's a fixed time of 300ns as well since that wouldn't make sense when running at +16MHz. So it depends on your clock speed.

Check the 6502 primer for more detail.
https://wilsonminesco.com/6502primer/

Yup, it will change with the clock speed, so I'm not relying on any exact delay. Many other CPUs I am more familiar with assert the address and data bus slightly *before* the read or write enable, or perhaps as the same time. Anyway, I still have to make changes and test, but I'm at least hopeful. I'll review the primer too, since it has been more years than I can remember since I looked at it.

@Paganini
Cool, good to know about AHC being a good middle ground. Thanks for the additional links.

[Paganini]

matthew180 wrote:

@Paganini
Cool, good to know about AHC being a good middle ground. Thanks for the additional links.

You bet! Since the conversation seems to have veered towards timing, here's another one: https://www.atarimagazines.com/computei ... /page9.php

This is a vintage article talking about vintage devices, but I think it's still really good. The concepts are still accurate; you just have to consider that with a 14MHz WDC65c02 tADS is 30ns and not 300ns!

[Dr Jefyll]

matthew180 wrote:

The 6502 has a very long (~300ns) delay from the time the R/!W goes low (for a write op) to when there is valid data on the data bus.

It's normal for R/W to go low early in the cycle. It'll change at more or less the same time the address bus changes.

Echoing what Proxy said, the /WR signal (sent to RAM, for example) shouldn't go be allowed to go active (ie, low) until Phi2 rises.

-- Jeff

[fachat]

Also, data should not be taken as valid even before the phi2 transition from high to low. Typically you take the data into a register when phi2 goes down. RAM typically has this property i.e. taking in the data at the end of the select

Pls look at the timing diagrams in the 6502 (and other related ICs) datasheet.