Ф2 sensitivity/noise

[and3rson]

I'm using ATF16V8 for address decoding, R/W qualification, & CPU underclocking (as I described here: viewtopic.php?f=4&t=7593#p100282)

PHV (pin 12, stands for Ф-variable) of my '16V8 goes directly to W65C02 only (VIA & friends use another clock signal from '16V8, pin 15). However, I've noticed that every time I touch this pin with tweezers or digital analyzer, my CPU goes haywire (reads/writes to random addresses, etc). I don't have a good oscilloscope and my logic analyzer has only 16 channels, so I cannot do full debugging on what's actually happening. It feels kinda similar to contact bouncing, as if high-frequency noise is being injected into clock line.
This issue also sometimes happened totally randomly when other ICs were enabled.

I thought crosstalk is involved so I cut the trace and connected '16V8 directly to W65C02 with a jumper to no avail.

Finally, I rerouted PHV through 2x 74HC14 and the issue is now gone.

All my ICs have 0.1uF bypass caps, and all power-hungry components have additional decoupling caps.

I'm running my system @ 8 MHz with a JCO-14 16 MHz crystal generator (PHV is either 8 MHz or 2 MHz, speed is controlled with /SLOW input).

Is W65C02 really that sensitive to Ф2 input?

[ttlworks]

Yes, it is.

W65C02S datasheet, page 24:
PHI2 Vih_min = VDD*0.7 //that would be Vih>3.5V at VDD=5V

ATF16V8B datasheet, page 5:
Voh_min = 2.4V
Voh_max isn't specified in the datasheet, but it might be below 3.5V when the ATF16V8B output pin is driving a load.

//At least your logic analyzer and your tweezers would be a capacitive load...


To be on the safe side,
I would recommend to place something like a 74ACT14 logic gate between the ATF16V8B output and the W65C02 PHI2 input.

//Note, that the W65C02 also seems to be sensitive to the rise/fall time of the signal at the PHI2 input pin.

[plasmo]

Take a look at section 11 of ATF1508B. You’ll see the output voltage can reach 4.1V with no load or 3.8V with 1mA load. I think the output can swing very wide and generate significant noise along the way. A source termination resistor of 75-100ohm may be helpful.
Bill

[ttlworks]

Bill, you are right:

There is a Voh diagram on page 18 of the ATF16V8B datasheet,
and I have missed it.

Source termination resistor is worth a try.

//It's an interesting question how much input capacitance the logic analyzer probe has
//(compared to a chip input pin) to make the circuitry behave differently...

[and3rson]

Dieter, Plasmo - thanks for the information!

I'll stick with '14 then, my SBC has been pretty stable so far with my spare 74HC14.

[BigDumbDinosaur]

plasmo wrote:

Take a look at section 11 of ATF1508B. You’ll see the output voltage can reach 4.1V with no load or 3.8V with 1mA load.

Yes, but...

The high end of that curve will be relatively slow-rising as parasitic capacitance is charged, and will likely violate WDC’s requirement that Ø2 have a max rise time of 5ns.

My opinion is a PLD should not be used as a clock source for any WDC product. A 74AC device will produce the most robust clock. 74HC or 74AHC may not have a fast enough edge to meet WDC specs.

[plasmo]

Since I do drive clock with CPLD, all the time, I probably should analyze the timing rather than just saying "but it works".

So rise time is the transition time from VIL to VIH which is 0.3VCC to 0.7VCC or 1.5V to 3.5V for W65C02. 2V in 5nS is 0.4V/nS slew rate. According to the chart above provided by ttlworks, at 3.5V the output can source 4mA into W65C02 clock input which has max capacitance of 5pF plus maybe 5pF of PCB trace for total of 10pF load capacitance. 4mA into 10pF happens to be 0.4V/nS slew rate so even at the weakest point of the output driver, it still can satisfy the 5nS rise time requirement.
Bill