Fast Discrete FET-Switch ALU

[Squonk]

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[BigEd]

Although the BCD correction circuit operates on nibbles, it is itself quite irregular. It needs to detect and to change the half-carry between the nibbles.

You'll also notice a lot of ALUs have different circuits for odd and even bits, and that's because the carry chain can be slightly faster (in some implementation styles) if it alternates between carry and not-carry with each bit.

So, a bit-pair might also be worth considering.

Good luck with the adventure!

[Squonk]

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[barnacle]

Don't forget that the z80 used a single 4-bit ALU twice, so two internal ticks; its ancestor the 8085 used an 8-bit ALU built from eight one-bit slices. But one other difference is that the 8085/z80 doesn't use the inverted borrow/carry that the 6502 does.

Neil

[Squonk]

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[Squonk]

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[Squonk]

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[BigEd]

One of the things about pass transistors - and I'm talking about NMOS on-chip circuit design, as elaborated in Mead & Conway - is that they don't have a simple propagation delay in the way that logic gates do. In fact, to a reasonable approximation, the propagation delay rises according to the square of the number of pass transistors in series.

So, for example, while the fastest adder circuit has logarithmic delay in the number of bits (5 units of delay for a 32 bit adder), and a normal carry chain with logic gates has linear delay in the number of bits (32 units of delay for a 32 bit adder), a carry chain built purely from pass transistors has quadratic delay (1024 units of delay for a 32 bit adder.

I don't know if these discrete devices behave similarly, but it might be worth an experiment.

Edit: of course an 8 bit machine is less affected by this than a 32 bit machine. Note that the 6502's 16 bit PC incrementer has a bit of lookahead to speed it up.

[Squonk]

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[Squonk]

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[barnacle]

Fascinating that e.g. HC family parts slow down as the supply voltage is reduced, yet the faster parts are lower voltage operating...

Watching this with interest...

Neil

[Squonk]

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[Squonk]

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[Squonk]

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[GARTHWILSON]

Squonk, a related recent topic is "Simplest subset of 6502" which you did not post in, so I don't know if you saw it.

Squonk wrote:

Most CPUs implement this set of hardware primitive functions to obtain a better efficiency:

• CLR: clear all bits (not supported by the 6502, but can be emulated by AND with a 0 value)

or LDA #0, or even LDX #0 or LDY #0, all taking two clocks, and two bytes, just as AND #0 does, but do not require the ALU.

Quote:

• ADD: arithmetic addition (not supported by the 6502; one must clear the carry CLC before an addition with carry)
• SUB: arithmetic subtraction (not supported by the 6502, one must set the carry SEC before an subtraction with carry)

IMO, if there aren't enough op codes available to implement all the addressing modes of the operations both with and without the carry flag, ADC and SBC are much more useful.  Even in single-byte arithmetic operations, there are many situations where you already know what the status of the C flag will be, and you don't have to set or clear it.  In multi-byte arithmetic, you don't want the SEC or CLC except for the first byte handled, ie, the low byte.

Quote:

This primitive operation set is often completed by derived operations, such as:

• [...]
• ROL: logical bitwise rotate left (supported by the 6502)
• ROR: logical bitwise rotate right (supported by the 6502)

and:

Quote:

Very often, arithmetic and rotations operations are derived in variants that include an input carry bit:

• [..]
• RLC: logical bitwise rotate left through carry (not supported by the 6502)
• RRC: logical bitwise rotate right through carry (not supported by the 6502)

Note that the 6502's ROL and ROR do rotate through C.