Practical debouncing - with pictures!

[barnacle]

To avoid cluttering this thread viewtopic.php?f=4&t=8383 further, I did some practical measurements and present the pretty pictures here. Comment and further analysis is welcomed!

The setup is simple: a 27k resistor (couldn't find a 47k) is connected between +5v and a generic Chinese 6mm square tact switch. The switch pulls the south end of the resistor to ground, so when the button is pushed, the output should fall to zero volts, and when released, it should rise back to 5v.

Here's what actually happens... note that this doesn't happen every time, but it happens often enough - one in four or five - that it needs attention.

This is triggered on the falling edge, but shows a bounce lasting around half a millisecond.

All these show a similar effect; a bounce occuring on the rising edge as the switch is released.

Well, ok, let's see what happens when you put that through a 74hc04. Some things to remember: this is a worst case situation; there is no decoupling on the '04, the remaining inputs are all unterminated, and of course as an hc type, the logic generically switches at half rail. These images are looking at the output of the '04, so the signal goes high when the button is pressed; the trigger is on the positive slope.

Again, there's disturbance at the end of the press - as might be expected, given the input signal.

Here, we see from the triggering point that there's a glitch about 2.5ms before the button is fully released.

This is a tight zoom into the falling transition - note that I'm still triggering on the _rising edge_. Not good.

OK, so let's stick a 100nF capacitor on the input to the '04 and ground. Here's the effect on a 5ms scale, input to the inverter.

But here's the output back at 200us

And finally, the cyan trace is the input and yellow the output as the switch is pressed and released.

The lack of hysteresis on the '04 input results in clear oscillation; we can't have that. I'm unable to test with a '14, but I think that the 100n/27k CR and a '14 will result in clean switching without a need for more complex software options.

Neil

[BigEd]

Excellent idea for a new thread!

I have a couple of bookmarks which probably fit here

• Comments in a previous discussion To build a keyboard…
• A Guide to Debouncing, or, How to Debounce a Contact in Two Easy Pages, by Jack Ganssle
• Switch Bounce and How to Deal with It, article on allaboutcircuits by Jens Christoffersen

[barnacle]

Jack Ganssle is an engineer who knows his stuff.

Looking at buffers with Schmitt trigger inputs... the 74HC14, of course, but it's an inverter. And various NAND options, but again, inverters. 74LS241/541 has Schmitt inputs, but the HC241/541 doesn't, which is irritating. 74AHC8541 offers similar pinout to the '541 and inverting or non-inverting outputs. 74HC9115 offers nine channels in a 20-pin package while AM29827 and AM29828 offer ten channels in a 24-pin package.

Or the OnSemi MC14490 is still available, but only in SOIC unless you want to go to Rochester and meet the minimum purchase requirements. That last is not a buffer but a hex bounce eliminator; one external capacitor to set the clock speed and you're sorted. However, be aware that it takes a low-going input and gives a high output while the switch is closed.

Neil

Edit: the AHC541 _is_ apparently Schmitt trigger, at least in the Nexperia version. For some reason that doesn't appear in the general description in the datasheet, and probably because of that, Digikey doesn't list it as a Schmitt part.
Edit: the AHC541 has no mention as Schmitt trigger in the TI version datasheet. However, TI does a DIP20 package, while Nexperia doesn't. I don't immediately find any far eastern copies, just those two makers.

[BruceRMcF]

Note that a ST inverter prior to the c/r circuit isn't an issue, since there are both "high if pressed" and "low if pressed" outputs available from the priority encoder, so an inverter in between just changes with keypress indicator to use. So if cleaning up the very highest frequency noise going into the c/r circuit helps (I don't know whether it would), that's kind of "for free" (given that it seems like U10 could be switched to a ST NAND with no problem for its existing use).

Adding ST inverter after, which seems like it's the stronger benefit, needs a simple c/r to flip whether the press is charging or draining the capacitor to maintain the same final output levels, and obviously I wouldn't even guess whether that makes things better or worse.

If the bounce gets down to somewhere between 1 in 50 and 1 in 100 keystrokes, then with a "back up one" function available, it seems like it might be tolerable.

The LogiSwitch LS18-P (3 line) and LS19-P (6 line) is still available Q1 from LogiSwitch, but Digikey lists them as a 5wk order, and obviously there's a shipping/handling fee.

[barnacle]

Neither the LS18/19 nor the MC14490 are suitable for use in a scanned array keypad, just for individual keys.

Because the output doesn't arrive until four clock cycles (so some milliseconds) after the actual keypress, there will be no output when a particular column is scanned, so the scan will move to the next column and appear to the debouncer as a permanently bouncing input; it will never trigger the output.

Neil

[BigEd]

Nice idea that backspace helps the user deal with a rare bounce.

I see the point of using Schmitt inputs if the input is slowly changing against a noisy ground reference, which it might be doing with a slow RC filter. But if they don't do the whole job - if software does some of it - maybe they are not needed.

[barnacle]

Probably worth keeping this thread for generic debounce issues, and the other for things relating to the DROM bios?

[BruceRMcF]

barnacle wrote:

Neither the LS18/19 nor the MC14490 are suitable for use in a scanned array keypad, just for individual keys.

{Head slap} ... of course, they would only work if the columns were simply selecting between sets of switches to read, not if the decrement through the columns is changing which switches are live ... with much less than 20ms dwell per column in unpressed state.