Okay, after much hemming and hawing over this I think I've finally settled with a design I want to go with.



I still need to layout the PCB for this, but I'd like to get some feed back on this to make sure I haven't done anything glaringly wrong.

Since you are using CPLD, you can consolidate the functions of 74163 and 7405 in the CPLD and eliminate two chips.
Bill

Thank you, I'll do that.

I presume I should leave the INT output from the CPLD floating in most situations until I'm ready to drive the line low? Is that correct for the 6502's open drain input?

Yes, you can simulate an open drain output by having the FPGA pin either float or drive low. (IOW, it never drives high.) There's no such thing as an open drain input, but probably you're referring to vintage peripheral IC's such as the 6522 which feature open drain outputs for the /IRQ pin.

For reasons explained about 20% of the way down this page in Garth's primer, open drain outputs can be problematic with faster systems, and it can be preferable to instead use an actual gate when it's necessary to combine interrupt signals,.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Excellent, good to know I was on the right track there.

Yea, I was aware of preferring the use of logic gates for the interrupts. The next design I do I'll use one of the PLCC packages; and I'll likely look at creating an actual interrupt decoder using the 74xx148 or something to that effect.

For now I'm trying to keep it as simple as I can.

CPLD also has open-collector primitive that can be added to an output. Alternatively you can add a tri-state buffer to the output with the tristate control wired to tristate buffer input thru an inverter. This way when tristate input is low, the buffer is enabled and drive the output low, but when input is high, the buffer is disabled thus the output float, to be pulled up by an external resistor.
Bill

So I've been fighting with the actual PCB layout for a while now. Seems like I have lots of wasted space and I keep having this nagging feeling in the back of my head that I'm violating some conventional wisdom of how to route things correctly.

This is where I'm at so far
(sorry for the color, but IDK how else to really present this)


Anyone have any advice?

Use tighter design rules, you should route 2 traces between IC pads. Pack the components as tightly as possible--should-to-shoulder. You can do it with 2 signal layers, other two layers can be power and ground planes. Use autorouter. If do it manually, don't be afraid of vias. Nothing wrong with using 5 or more vias to get a signal routed. Since it is all DIPS, you can actually do all routings with just 2 layers, but 4-layer pcb are so cheap, I'd go for 4-layer board.
Bill

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?