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PostPosted: Wed Nov 29, 2023 11:12 pm 
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Joined: Sun Sep 24, 2023 3:45 pm
Posts: 47
Hi all!
I’ve got my Ben Eater 6502 and Worlds Worst Video card kits and I wanted to add double buffered video to my system as easily as I could.
I read everything I can around here and at Wilsonminesco.com and I did a lot of Altavista queries, checked out Usenet, did some Gopher library browsing, logged into my local BBS, the usual…..
Anyway, I figured it out.
But I sure spent a lot of time on the memory setup.
One thing is that wanted to add to my system while keeping the memory mapping of the existing hardware the same while adding this Double Buffered Video.
The Ram is right there. 16 juicy kilobytes sitting unused.
I just needed to access it!

The 1 chip NAND decoding used in the system is so clever because it does so much with just the one chip. 16K RAM, 32k ROM, and a VIA and ACIA (or more!) all decoded and ready to go with the 1 chip.
Doing anything to improve on it adds to the build pin count quite a bit and leaves unused gates.

But…
To add a double buffer to my VGA setup I needed to use some of the unused upper 16k of the 32k SRAM.
The problem is the NAND decoding setup writes to RAM when you write to your IO chips in the IO address range. No problem if you never read or show that RAM!
Now that I do, another NAND gate, and a NOR gate fixes it.

With that in place a AND,XOR,and OR gate each get me a setup where I can enable or disable Double Buffered video and change the displayed buffer with a couple of VIA pins. The ‘off screen’ video ram is always presented to the system as being 8kb at location $2000 and the circuit shows the ‘on screen’ memory without any intervention.
I’m pretty happy I figured this one out. Just a few cents of 74 series chips and a huge enhancement in the video capabilities!

Attachment:
File comment: Double Buffered VGA and Mem Map Fix
NormalLuserBEMemMapFix.png
NormalLuserBEMemMapFix.png [ 215.65 KiB | Viewed 3098 times ]

I’m also looking to put some Dual Port RAM hooked up to a character display circuit in the near future.
There are two ways I could do this;
In the same address space as the ROM so that writes to $8000+ are blind writes to the character screen, and reads are still reads from ROM.
That won't work as is because the ROM will be outputting when that range is accessed for writes.
Another NAND gate on the Read/Write line used as an inverter and used as the ROM Output Enable fixes that issue.

Likewise, if I wanted to put 4k of Dual Port RAM at address $7000 the VIA will get selected.
That takes yet another NAND as a inverter and a OR to fix.

I really see why folks eventually play with a PLD for address decoding, but I still like how easy it is to do quite a lot with just a few 74 series chips.

The added 4 74 series chips, and a few gates already present get the mods on the attached image done.

I’m pretty happy with the results!
Attachment:
File comment: Lets Scroll software sprites using a Double Buffer!
DoubleBufferScroll.gif
DoubleBufferScroll.gif [ 6.08 MiB | Viewed 3098 times ]


I'm really on this kick to see just how much can be done with as little as possible.


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PostPosted: Thu Nov 30, 2023 12:57 am 
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Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741
Thanks for sharing more details. It is nice and educational to do address decoding using primitive gates, but I think there comes a point where it's worth using a more integrated address decoder like 74HC138 or 74HC139 - have you considered that? 74HC139 is also great for generating the PHI2-qualified RAM read/write signals, you can use one half of the IC for that and the other half for some address decoding.


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PostPosted: Thu Nov 30, 2023 5:26 am 
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Joined: Sun Sep 24, 2023 3:45 pm
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gfoot wrote:
a more integrated address decoder like 74HC138 or 74HC139 - have you considered that?

I did when I was first trying to expand and had issues that I'm sure were unrelated. I should revisit how I can reduce the chip count using them.


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PostPosted: Thu Nov 30, 2023 6:48 am 
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Joined: Tue Feb 28, 2023 11:39 pm
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Location: Texas
NormalLuser wrote:
gfoot wrote:
a more integrated address decoder like 74HC138 or 74HC139 - have you considered that?

I did when I was first trying to expand and had issues that I'm sure were unrelated. I should revisit how I can reduce the chip count using them.


I actually first used the '138 and '139s in my design after watching Eater's videos and they worked out better for me. It helped that I was okay with remapping the memory around some. Specifically I have all 32KB of RAM usable for general purpose computing, and then divided the upper portion into 4 8k banks with the 8 KB ROM that I had in the upper slot. This has left me with lots of area for playing around with other devices w/o sacrificing my 32KB of RAM.

The '139 further divides one of those four banks into 8 smaller segments for memory mapped I/O.

I never got around to making the video card portion of his designs yet. I was considering something like a double buffer approach as well as some DMA ideas. (To be honest I won't be happy till I get some good SNES style sprites working :mrgreen: )

I think you could hook up a 74HC74 to the vblank signal and have it automatically switch the banks for you, if I'm understanding your design correctly.


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PostPosted: Thu Nov 30, 2023 11:47 am 
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Joined: Sat Oct 09, 2021 11:21 am
Posts: 718
Location: Texas
NormalLuser wrote:
I’m pretty happy with the results!


That's really good looking! Great job, thank you for sharing!

Chad


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PostPosted: Sat Dec 02, 2023 11:33 pm 
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sburrow wrote:
NormalLuser wrote:
I’m pretty happy with the results!


That's really good looking! Great job, thank you for sharing!

Chad

Thanks!
I plan on several more documented enhancements eventually.
I really hope someone finds them helpful someday.


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