I'm seriously confused here so diving right in...

Programming the 65816 says:

The WDC65C816 datasheet says:

In BDD's INVESTIGATING 65C816 INTERRUPTS page he says:

My question is on the italicised bits. Does the 65816 bail out of the current instruction even if it still has a few cycles to complete? Or does it run to completion like it would in every other interrupt except reset?

The first would make more sense because I don't see how else it would stop doing memory accesses during the aborted instruction.

The second would make sense because it follows every other interrupts pattern (except reset) of completing the current instruction first before the interrupt occurs. But what if the aborted instruction is a write? Does RWB go high to stop the write? And what about all the addressing reads? Do VPA and VPB go low during the rest of the instruction to indicate memory shouldn't read?

Checking out Sam Falvo's lib65816 isn't helpful because emulation is done at an instruction level, not a cycle level. And Francesco Rigoni's lib65816 is even less helpful as it doesn't handle abort at all.

As always any enlightenment would be most appreciated!

I suspect you'd need someone to take some measurements. WDC's documents are at best a guide.

My guess would be that all cycles complete, that writes are changed to reads, and the valid signals stay low (to indicate an internal operation) - but my guess is just a guess.

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Thanks, that's most helpful! You've opened up a whole lot more timing questions that I'm going to need draw out before I can ask them.

Ta, I'm going to make this assumption for now (as far as finishing up the emulator goes). I'll definitely need to break out the soldering iron later and do a bunch of measurements.

...and here they are: my questions are around the timing of specifically the ABORT and IRQ interrupts because they're level triggered.

If you take a look at the picture below (really just the Instruction column) you'll see I've sketched in the clock with time increasing from top to bottom.



Where is IRQB latched in the 65816? I've made the assumption that it is every falling clock (high-to-low transition). But is that right? Or is it only the very last cycle in the instruction? (In this example would it be only 5H-to-5L?) Again I'm assuming; the point at which the 65816 tests if an IRQ has occurred must be on the final low-to-high clock transition in the instruction? In this example 5L-to-1H before the next op-code fetch.

And when is ABORTB latched? I'm guessing it is also on each falling clock as it must be tested on each rising clock in the instruction?

I really think we need to measure this: the documents, and Bill's recollections of intent, are not definitive.

Edit: for this level of detail, as to what happens in each cycle, there's a lot to be learnt from this thread:
A taken branch delays interrupt handling by one instruction

It's about the 6502 not the '816 but it demonstrates that no simple statement is true - the reality is complicated!

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http://WilsonMinesCo.com/ lots of 6502 resources
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Thanks, that was in interesting read. It's giving me (small) nightmares about what will happen when finally get into the hardware side of things.

Thanks for spotting that! I think I melted my brain whilst sorting out weird Logisim emulation issues because I really should have known that.

Also it was good to know about IRQ and ABORT, thanks. I'm going to take a 'good enough' approach to emulating them as I hadn't realised how complicated the 65816 really is. I've simplified down to the code below for now.



(In the case where IRQs are disabled but irq is set I clear irq just before the test for it is done. Probably not how things really work but close enough for now)