Yes, they are multiple people following along the videos and trying their own thing. I think it is great. I'm doing this to inspire others to build their own



Thanks! I'll improve my ground distribution at some point

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BB816 Computer YouTube series

In other news, Episode 19 is out!

I'm pretty happy with the result of this episode. My read-write pulse generation is now working great and is also completely within spec on the timings. I did need to add the complexity of a third clock phase (this one shifted 20ns before the clock), but the circuit now takes into account all the control signals of the CPU (VDA, VPA, RDY, BE). I expect this clock phase to go away once I move to a fast SPLD but still, doing it in discrete logic was a fun challenge.

Here is what it looks like now

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BB816 Computer YouTube series

Glad you're enjoying the journey! And it's a hobby project, so of course you get to pursue whichever goals seem most gratifying to you.

Still, it seems odd that you haven't followed up on the signal integrity problems you were asking about over a month ago. Seems to me you have another fun (and potentially educational) challenge awaiting you! And there's low hanging fruit, in the sense that your Power/Gnd network has some gross deficiencies, the worst of which could be remedied in a matter of minutes.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I want to batch it in an episode with other small tasks. Getting to the end of the glue logic arc was important, otherwise, if I go in and out of subjects I risk people forgetting what I'm talking about. It's not too bad for now as I'm not doing anything with the CPU, and mainly working on the hardware. I think I'll do it with the extended RAM, which might be one of the next episodes!

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BB816 Computer YouTube series

Okay -- one step at a time, I guess. It won't take long to fix the gaps in your Power/Gnd grid as I suggested. Likewise it'll be pretty easy to add a ground wire running adjacent to your big, long data-bus bundle, connecting to local ground at each end.

It'll be good to see these issues illuminated, particularly since your video series has an educational slant. Breadboards are understandably attractive to novices, but it's important be mention at least the most basic -- and lazy! -- techniques for staying out of trouble.

AC performance is a deep subject, but probably the biggest bang for your buck if further improvement is still necessary is the connections to bypass capacitors. It's important to keep these short, and the obvious solution is to straddle the chips (more or less as shown in the photo).

I would begin by attending to the CPU and RAM chips. Because these are among the most critical (for reasons including the multiple simultaneously switching outputs), you may find that no further improvements are necessary.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

(I'd love to see a careful analysis, with scope traces, of the effect of this sort of micro-optimisation, of reducing lead lengths by a few tenths of an inch, or a few tens of percent. It feels to me like a step too far, in the sense that it's almost always of no practical benefit, but I haven't done, or seen, an analysis, so that's merely an opinion.)

In some contexts the question of excess fussiness might be supportable, Ed, but in this case we're not quibbling over tenths of an inch.

Have you had a close look at this builder's existing wiring for bypass caps? (Unfortunately it's roughly on par with other breadboard projects we've seen.) And are you forgetting that he's reporting stability problems (and has asked for suggestions)?

In comparison with what's there now, the technique I illustrated is very far indeed from a "micro" optimisation.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Yeah, I know that my decoupling capacitors do little on my breadboard, wired as they are. I haven't been able to straddle them so far because I had specimens with really short leads. I might look into getting some with longer leads! Alternatively, I'm also looking at moving to PCBs soon-ish, which is part of why I was procrastinating a bit on fixing this issue.

However, you should know that in the last episode (which I will announce below), I updated the ground distribution following your recommendations, Dr Jefyll, and you got a mention (starts at 18:18) Stability is now much better, so thanks!

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BB816 Computer YouTube series

Episode 20 is out!

In this video, I add 512K of extended RAM to the computer, making use for the first time of the extended address space of the 65C816. Additionally, I improve the ground distribution on the breadboards and work on speed optimization for the Teensy monitor.

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Ahem, yes, sorry, I rather missed the point. I was comparing the two over-chip caps in your picture, Jeff, where there is a very small difference between the relatively conventional and the micro-optimised.

I completely agree, of course, that bypass caps are needed and need to be pretty well connected to the chips in question, and also, of course, that power and ground need to be solidly routed and connected.

(I don't like phrases like "as close as possible" because they don't quite convey the real tradeoffs.)

I'd opine that they increase the stability of your build, even wired as is. I've seen many breadboard builds that were unstable without decoupling capacitors. It's an easy test. Take your decoupling capacitors off and see if your build still runs.

@akohlbecker I like your test-driven approach, and validating all the steps (according what I read from the forum, just discovered the thread, haven't seen the videos yet). I'm more into rule-of-thumb calculations and that sometimes bites me...

btw, if you think about going to DIN41612 - you may have a look at this 6502/816 bus design here based on it http://www.6502.org/users/andre/csa/bus-1.1.html
It would be cool if someone else besides me would actually use it and we could share boards....
(sorry 'bout the self-plug, but the mentioning of the DIN triggered it)

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

So, there are multiple types of carbon resistor and they have differing inductance and accuracy. As a relative newbie to electronics, I have looked at a parts catalog and think "Can y'all get together and reduce the types of resistors and capacitors which are available. While you do so, could you also reduce the number of sizes." I don't say this lightly. I come from hydroponics where every legacy light-bulb fitting has an LED retro-fit and a choice of light spectrum. I suppose this is economics in action. They wouldn't make them unless someone wanted them.



Someone (rehsd?) was considering a retro project of interfacing 6502 to open reel tape for storage. I thought this would be easier than compact cassette on the basis that larger tape at higher speed would be better quality. However, if it uses 1970s amplifiers or older then open reel might be more difficult. As I understand, the failure of the quadraphonic standards, such as QS and SQ, was due to cross-talk and poor amplification. Nowadays, we have the luxury of Dolby 7.1 and the 3D audio formats, This is possible due to digital storage, digital processing and cheap, compact linear amplifiers (because you'll need eight or more of them).

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Modules | Processors | Boards | Boxes | Beep, Beep! I'm a sheep!

I wonder if a pair of 74HC688s could be used to "insert" ROM and I/O into the 64K Bank 0 address space for a simple 512K system? Would they limit the clock speed and what signals need to be qualified by VDA & VPA?

Hey! It would probably work, but it will be slow if you use HC logic. Unfortunately, no comparators are available in faster logic...

From your diagram, here is what I can gather

- You're relying on the /OE pin in the comparators for B0. This will slow your logic a lot because you'll be limited by the pull-up time constant for /IO and /RO, when they are tri-stated
- Speed of B0 will depend on your latching circuit, which you haven't included. I'll assume a HC family 573 in my calculations. That one takes 44ns over temperature to propagate when it is transparent. Adding the time the CPU needs to put the Bank Address on the bus (33ns), you get 77ns for A16-A23.
- The 74HC4072 then takes 25ns. So B0 takes 102ns.
- The 74HC688 then takes 30ns to propagate its /OE pin, and 42ns to propagate the inputs. A0-A15 take 30ns to be put on the bus so they're not limiting here (30+42 < 102). That means that /IO and /RO both take 102ns when they're asserted. As I said when B0 goes high it depends on the stray capacitance and pull up strengh.
- The 74HC138 then takes 38ns to propagate /E1. Addresses here are not limiting since that takes also 38ns, but they're here at 30ns. So /IOx takes 140ns.

Now for the RAM/ROM,
- RW takes 30ns, and the 74HC139 takes 36ns, so /RD and /WR take 66ns.
- Similarly, /RAM and /ROM take 102+36 = 138ns

So, for the clock
- a 65C22 needs its chip select 10ns before the rising edge of the clock. So the half period can't be below /IOx+10ns, so 150ns. So clock < 3,33Mhz
- the flash rom, assuming a 70ns model, outputs data 70ns after chip enable, so 70+/ROM = 208ns, and also 35ns after /OE so 32+66=98ns. You haven't specified the buffer but a 74HC245 will take 26ns to propagate, and the CPU needs the data 10ns before the falling edge of the clock, so the clock can't be below 208+26+10 = 244ns. That's 4,1Mhz
- A similar calculation can be made for the RAM in a read cycle, assuming a 55ns model, We get a slightly faster clock at 4,3Mhz
- The write cycle is not going to work in spec here, because we would need /WR to take less than 10ns after the falling edge of the clock. Probably won't be ok at 36ns

All in all, this would limit you to 3,33MHz if you include a VIA, 4Mhz with no peripherals, and the RAM would probably not register writes properly.
This, of course, is only the worst case to be in spec. Overclocking it quite a bit could be possible!

Regarding VDA and VPA, you need to protect I/O reads (I don't think the CPU ever writes with both set to 0, and RAM/ROM are fine with unexpected reads). So I would OR them and connect the result to E3 on the 138. I don't think that would impact the frequency as B0 is really the limiting factor.
I would replace the HC139 by an AHC139, that one takes 10.5ns worst case, so the RAM would probably be fine with /WR at that speed!
/IO and /RO need strong pull-ups as they can be tri-stated, 1K should be fine, I measured ~30ns in my RDY circuit with a similar scheme.
This scheme also presumes you're not going to be using BE or RDY. If you are then it needs a lot of changes.

I quite enjoyed looking at this circuit. Hopefully this is helpful to you!

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BB816 Computer YouTube series