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PostPosted: Tue Oct 19, 2021 5:28 pm 
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I'm seriously confused here so diving right in...

Programming the 65816 says:
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The ABORT’ input pin, when it is asserted, causes the current instruction to be aborted. Unlike an interrupt, none of the registers are updated and the instruction quits execution from the cycle where the ABORT’ signal was received. No registers are modified. In other words, the processor is left in the state it was in before the instruction that was aborted. Control is shifted to the ABORT’ vector after an interrupt-like context-saving cycle.

The WDC65C816 datasheet says:
Quote:
A negative transition will inhibit modification of any internal register during the current instruction. Upon completion of this instruction, an interrupt sequence is initiated. The location of the aborted opcode is stored as the return address in stack memory.

In BDD's INVESTIGATING 65C816 INTERRUPTS page he says:
Quote:
It should be noted that despite the interrupt's name, an "aborted" instruction isn't actually aborted—all steps of the instruction will be completed before the 65C816 reacts to the interrupt. What is aborted are computational changes to a register and/or memory that the instruction would have made had it not been "aborted."

My question is on the italicised bits. Does the 65816 bail out of the current instruction even if it still has a few cycles to complete? Or does it run to completion like it would in every other interrupt except reset?

The first would make more sense because I don't see how else it would stop doing memory accesses during the aborted instruction.

The second would make sense because it follows every other interrupts pattern (except reset) of completing the current instruction first before the interrupt occurs. But what if the aborted instruction is a write? Does RWB go high to stop the write? And what about all the addressing reads? Do VPA and VPB go low during the rest of the instruction to indicate memory shouldn't read?

Checking out Sam Falvo's lib65816 isn't helpful because emulation is done at an instruction level, not a cycle level. And Francesco Rigoni's lib65816 is even less helpful as it doesn't handle abort at all.

As always any enlightenment would be most appreciated!


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PostPosted: Tue Oct 19, 2021 7:04 pm 
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I suspect you'd need someone to take some measurements. WDC's documents are at best a guide.

My guess would be that all cycles complete, that writes are changed to reads, and the valid signals stay low (to indicate an internal operation) - but my guess is just a guess.


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PostPosted: Tue Oct 19, 2021 8:20 pm 
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AndrewP wrote:
I'm seriously confused here so diving right in...

The statement made in the 65C816 interrupts article is correct.

Asserting (i.e., negating) ABORTB does not abort the current instruction—all steps will take place.¹ What is aborted is any computational change that would have otherwise occurred to a register or memory. The initial response to ABORTB being asserted occurs while the current instruction is still executing, which is unlike that of IRQB or NMIB—those are not sampled until the final step of the current instruction has been completed and the clock falls.

Following the "aborting" of the current instruction, an interrupt sequence is initiated. The abort interrupt sequence is essentially like that of any other interrupt, in that the MPU state is pushed, interrupts are disabled and the abort hardware vector is taken. The key difference is the address pushed to the stack is that of the aborted instruction, not the next instruction, as would be the case for the other interrupt types. This means a properly-crafted abort interrupt handler can "fix" whatever caused the abort and then re-execute the "aborted" instruction as though nothing had happened. That's the theory, anyhow.

The use of ABORTB is very much timing-sensitive, more so because it is a level-sensitive input (it should have been edge-sensitive). If ABORTB is asserted too long the abort interrupt sequence will itself be aborted and may result in unintended changes to registers and/or memory. My study of the 816's response to ABORTB tells me ABORTB should be driven low for only one clock cycle to avoid anomalous behavior. The 65C816 timing diagram has it being asserted shortly before the rise of Ø2, which is probably the ideal time to do so. In any case, the hardware responsible for controlling ABORTB must make sure the input is asserted only once during the instruction cycle.

All of this information was confirmed during conversations with Bill Mensch, the designer of the 65C816.

——————————
¹An unfortunate byproduct of this behavior is the STP and WAI instructions will stop the MPU despite having been aborted.

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PostPosted: Wed Oct 20, 2021 11:19 am 
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BigDumbDinosaur wrote:
ABORTB does not abort the current instruction—all steps will take place.¹
Thanks, that's most helpful! You've opened up a whole lot more timing questions that I'm going to need draw out before I can ask them.

BigEd wrote:
My guess would be that all cycles complete, that writes are changed to reads, and the valid signals stay low (to indicate an internal operation).
Ta, I'm going to make this assumption for now (as far as finishing up the emulator goes). I'll definitely need to break out the soldering iron later and do a bunch of measurements.


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PostPosted: Wed Oct 20, 2021 1:23 pm 
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...and here they are: my questions are around the timing of specifically the ABORT and IRQ interrupts because they're level triggered.

If you take a look at the picture below (really just the Instruction column) you'll see I've sketched in the clock with time increasing from top to bottom.

Image

Where is IRQB latched in the 65816? I've made the assumption that it is every falling clock (high-to-low transition). But is that right? Or is it only the very last cycle in the instruction? (In this example would it be only 5H-to-5L?) Again I'm assuming; the point at which the 65816 tests if an IRQ has occurred must be on the final low-to-high clock transition in the instruction? In this example 5L-to-1H before the next op-code fetch.

And when is ABORTB latched? I'm guessing it is also on each falling clock as it must be tested on each rising clock in the instruction?


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PostPosted: Wed Oct 20, 2021 2:25 pm 
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I really think we need to measure this: the documents, and Bill's recollections of intent, are not definitive.

Edit: for this level of detail, as to what happens in each cycle, there's a lot to be learnt from this thread:
A taken branch delays interrupt handling by one instruction

It's about the 6502 not the '816 but it demonstrates that no simple statement is true - the reality is complicated!


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PostPosted: Wed Oct 20, 2021 6:44 pm 
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AndrewP wrote:
If you take a look at the picture below (really just the Instruction column) you'll see I've sketched in the clock with time increasing from top to bottom.

Each cycle of 65xx starts with phase 2 low, not high. It's low when it is setting up the address, R/W, ML\, VP\, VDA, and VPA. It is high for the second half of the cycle, not the first.

Quote:
Where is IRQB latched in the 65816? I've made the assumption that it is every falling clock (high-to-low transition). But is that right? Or is it only the very last cycle in the instruction? (In this example would it be only 5H-to-5L?) Again I'm assuming; the point at which the 65816 tests if an IRQ has occurred must be on the final low-to-high clock transition in the instruction? In this example 5L-to-1H before the next op-code fetch.

In my tests a few years ago, if I pulled IRQ\ down in the middle of the high (second) half of the operand-fetch cycle of a conditional-branch instruction that was to be taken, it would take the branch, but load and discard the first op code at the new address. I'm sure I have more test results somewhere, which I'm not able to find at the moment, to see if pulling it low during the op-code fetch would keep it from even taking the branch. Same thing below. I'm just looking at scans of the some of the printouts I have in a file somewhere. I know it's pretty incomplete, but hopefully it will still be of some help.

Quote:
And when is ABORTB latched? I'm guessing it is also on each falling clock as it must be tested on each rising clock in the instruction?

When I pulled ABORT\ low during a TXY op-code fetch, in the middle of the high (second) half of the cycle, it would fetch the next address in its dead cycle (since TXY is a one-byte, two-cycle instruction), then fetch the next instruction again as if it were going to execute it, but would discard it, then have another dead bus cycle, then head into the ABORT\ sequence.

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PostPosted: Thu Oct 21, 2021 2:37 pm 
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BigEd wrote:
Edit: for this level of detail, as to what happens in each cycle, there's a lot to be learnt from this thread: A taken branch delays interrupt handling by one instruction
Thanks, that was in interesting read. It's giving me (small) nightmares about what will happen when finally get into the hardware side of things. :shock:

GARTHWILSON wrote:
Each cycle of 65xx starts with phase 2 low, not high. It's low when it is setting up the address, R/W, ML\, VP\, VDA, and VPA. It is high for the second half of the cycle, not the first.
Thanks for spotting that! I think I melted my brain whilst sorting out weird Logisim emulation issues because I really should have known that.

Also it was good to know about IRQ and ABORT, thanks. I'm going to take a 'good enough' approach to emulating them as I hadn't realised how complicated the 65816 really is. I've simplified down to the code below for now.

Image

(In the case where IRQs are disabled but irq is set I clear irq just before the test for it is done. Probably not how things really work but close enough for now)


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