Just want to double check something with y'all.
Namely, I've got an SPI MISO line going into VIA input pin PB7, which is connected to two SPI devices. One device is 5V, the other 3.3V. The VIA (and most of the system) are on 5V.
My concerns are twofold:
1. According to the VIA datasheet, to be recognised as a logic high the signal must be Vdd X 0.8... 5V x 0.8 = 4V which is 0.7V too high for 3.3V. Now, I believe that that the VIA datasheet is conservative in many of its numbers, and -normally- CMOS inputs can cope with logic highs as low as 2.7V with Vdd=5V, so I suspect that actually it'll work with 3.3V=High fine, but I want to see if anyone has any experience? If it won't, then I need to translate the 3.3V up to 5V.
2. When the 5V device is selected, the 3.3V device will tristate its MISO pin. I'm therefore believe that the 5V won't get into the 3.3V device and blow up its internals, but again I'm not certain. Unfortunately the datasheet for the 3.3V device does not specify if it is 5V tolerant when tristated.
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