Dr Jefyll wrote:
Do I seem to be coming on too strongly? My very first words were, "The transceiver can be omitted."
But there's an attendant compromise. IMO, builders who are less experienced than you would be well advised to include the transceiver, and even seasoned veterans should think twice before dispensing with it.
My POC V1 design was built without the bus transceiver and was stable at 15 Mhz without the SCSI host adapter being plugged in. I never dug into the timing far enough to determine if it was due to sheer, dumb luck or due to the conservative nature of the '816's design.
There's no question that a risk of bus contention exists at the transition from Ø2 low to Ø2 high. The '816 timing diagram implies that the bank bits persist beyond the transition, apparently by
tBH, which is 10ns on 5 volts, if one can believe the AC characteristics data chart. This means, of course, the data bus is still being driven by the '816 after the rise of Ø2, apparently for 10ns (worst case). Assuming a read operation is gated by Ø2 high, the lag between Ø2 high and the presence of device output on D0-D7 will be determined by the gate prop time needed after the low-to-high transition of Ø2 to generate the "read data" signal (e.g., /RD) at the addressed device plus the time required for the device to respond to negation of /OE and start driving the bus. If that cumulative time is equal to or less than
tBH some contention will occur.
In revisiting my POC V1.1 design, my read/write circuitry's total prop time from the rise of Ø2 to when /RD goes low is a single gate delay caused by the 74AC00 NAND that drives /RD (see below).
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Best-case prop time on the 'AC00 at 5 volts is 1.9ns (worst case is 6.6ns), which means /RD would go low before the expiration of
tBH (even at worst-case performance, /RD would be low before the expiration of
tBH). The fastest device in the system is the SRAM, which can switch from hi-Z to active mode in 6ns or less when its /OE is negated. Doing the math suggests the SRAM could start driving the bus before the expiration of
tBH—bear in mind that as soon as the SRAM comes out of hi-Z it is a bus driver. This would come about if the NAND and the SRAM are both operating in the middle of their respective limits.
How would a transceiver help? In itself, it probably won't, assuming my timing assumptions are correct. The typical prop time for a 74AC245 transceiver ranges from 1.0ns to 9.0ns with Vcc being 5 volts. The device's output enable time ranges from 1.5ns to 8.5ns, again with Vcc = 5. Even in worst-case conditions, the 'AC245 is faster than
tBH. The key here, I think, is in realizing that as soon as the transceiver responds to its /OE it becomes a bus driver and hence a bus contender until
tBH has elapsed.
It would appear that total avoidance of contention requires that the transceiver itself be made to lag the rise and fall of Ø2 by an amount equal to
tBH, plus a nanosecond or two for good measure.
This would appear to contraindicate directly gating the transceiver's /OE from Ø2.
In my application in POC V2.2, I used the /Q output of the main clock flip-flop to drive the transceiver's /OE, but now feel that may have not been the correct path to take. Even in worst case timing, it would cause the 'AC245 to come out of the hi-Z state before the elapse of
tBH. If so, the resulting egregious bus contention, as Jeff suggests, could result in an unstable or DOA unit (I don't know at this point which applies to POC V2.2).
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