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 Post subject: 6522 vs. WDC 65C22
PostPosted: Thu Oct 09, 2003 5:06 pm 
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I am having trouble interfacing my VIA's IO ports to latches. I have Port A wired as a data bus, feed two 74LS373's and one 28256 EEPROM's data port (a simple EEPROM programmer).

The 74LS373's latch high and low address bytes, which are output to the EEPROM address pins. Port B is used to latch the 74LS373 and control the EEPROM's /CE, /OE, and /WE pins.

When I run with a MOS 6522 @ 2MHz, everything works great. When I change to a new WDC65C22, I get random errors. I tried it at 1MHz and at 4MHz with the same results. I've tried to insert NOP's all over the code to ensure enough time between control line changes with no change.

In my code, I disable the EEPROM, set an address on PORT A, and toggle the bit on Port B that controls the 74LS373 latch. Do the same for the other latch, and then enable the EEPROM. I can then either read or write to it. What happens is that some bytes (random) do not program properly. I am following the proper programming procedures, as evidenced by the MOS 6522 working.

Now, I use a very similar setup on my video test circuit and am getting the same indications there. The MOS 6522 will refresh the display perfectly every time. The WDC part gets random bytes that are not properly written.

I'm think its a hardware issue. Either too many LS parts connected to Port A or something along that line. Also, could writing to Port B cause noise during the transition. I am only changing one bit at a time, but could other bits be pulsing?

Does anyone have any suggestions? Unfortunately, all I have for test equipment is a simple logic probe and a DVM.

Thanks!

Daryl


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PostPosted: Thu Oct 09, 2003 9:31 pm 
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I replaced a Rockwell 65c22 with a WDC one this week and had no problems. This VIA is used for lots of things in my workbench computer, and they all worked fine. Clock speed is 5MHz.

The main difference of course is the totem-pole IRQ output as we discussed earlier. If you have something else trying to pull the IRQ line down while the new WDC VIA is trying to keep it high, that may cause a problem. If there are other open-drain IRQ outputs connected to the same IRQ line, you'll need the diode.

As far as output current, I found the WDC VIA to be able to pull down to a valid TTL logic-low level with about 24mA, and up to a valid TTL logic-high level with about 40mA. Especially if excessive fan-out might be a problem, I'd dump the 74LS parts and use at least HC or HCT if not AC. People keep saying HC is slower than LS, but I keep going back to the data books and finding that that's not generally true. Yes, with some parts, it's marginally slower, but with other ones it's significantly faster. There's not a lot of difference though, and it sounds like either one is plenty fast for what you're doing. AC is quite a lot faster than either LS or HC.

The WDC part is much faster than the MOS part. Even if you hold the clock speed down, the edges are fast and the resulting ringing and crosstalk may cause problems if the circuit construction is only suitable for 1MHz parts.

I know you already have it built, but this kind of circuit would be less work to build and leave you with more I/O pins if you use the VIA's serial port to feed a daisychain of 74HC595 8-bit serial-to-parallel shift registers, at least for the 16 address lines. I've used this kind of thing to get hundreds of output bits from a single VIA.

Garth

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Last edited by GARTHWILSON on Thu Feb 23, 2006 8:48 pm, edited 1 time in total.

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PostPosted: Fri Oct 10, 2003 2:19 pm 
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GARTHWILSON wrote:
The main difference of course is the totem-pole IRQ output as we discussed earlier. If you have something else trying to pull the IRQ line down while the new WDC VIA is trying to keep it high, that may cause a problem. If there are other open-drain IRQ outputs connected to the same IRQ line, you'll need the diode.


I read in the 6522 article by Bill Mensch (located on this site) that all I/O pins on the 65C22 use the same basic buffer design. Consequently, the I/O pins are also totem-pole, whereas the Rockwell unit is open-drain.


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PostPosted: Fri Oct 10, 2003 3:53 pm 
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Quote:
I read in the 6522 article by Bill Mensch (located on this site) that all I/O pins on the 65C22 use the same basic buffer design. Consequently, the I/O pins are also totem-pole, whereas the Rockwell unit is open-drain.

I believe the MOS ones were similar to a standard LSTTL-type output. IOW, they can pull up, but not nearly as hard as they can pull down. I don't have a MOS data sheet, but it may be available on this website. Regardless of what Rockwell's data sheet says however, I found from experimentation that the Rockwell VIAs will give 15-20mA per bit pulling up if you short them to ground, and around 100mA per bit pulling down if you short them to +5V. In constrast, WDC's design is balanced at about 50mA each way. With a 220-ohm load to ground (still an unusually heavy load), the Rockwell VIAs can pull up to hardly more than 2.25V (10mA), whereas the WDC VIA can pull the same load up to over 4.2V (19mA).

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What's an additional VIA among friends, anyhow?


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PostPosted: Fri Oct 10, 2003 4:11 pm 
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GARTHWILSON wrote:
In constrast, WDC's design is balanced at about 50mA each way. With a 220-ohm load to ground (still an unusually heavy load), the Rockwell VIAs can pull up to hardly more than 2.25V (10mA), whereas the WDC VIA can pull the same load up to over 4.2V (19mA).


Based on what you wrote, I calculated the impedance (for lack of better word) to be 100 ohms for the WDC part. So adding 220 ohms to 100 ohms results in 320 ohms. Across a 5V supply, that gives a current flow of only 15.6mA, which results in a total output voltage of 3.4V or so.

How did you get 4.2V at 19mA? That implies an internal resistance of about 43 ohms or so. If that is indeed the case, then shorted one way or the other, the WDC part ought to draw (or give) a monsterous 116.25mA -- almost 3 times the amount you specified.


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PostPosted: Fri Oct 10, 2003 9:08 pm 
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Hi 8Bit,

What CPU are you using?

If it's an NMOS 6502, maybe the CMOS 65C22 requires a CMOS
logic level on the data-bus. If so, you could try adding pull-ups
to the data-bus or switch to a 65C02 CPU.

Also, since the 65C22 is CMOS, it requires more capacitance close
to the chip and a better ground connection. CMOS chips draw less
average current but are more "spiky" on their current draw and hence
require more capacitors.

Hope this helps.

Bye,

Paul


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PostPosted: Fri Oct 10, 2003 10:22 pm 
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> Based on what you wrote, I calculated the impedance (for lack of better
> word) to be 100 ohms for the WDC part. So adding 220 ohms to 100
> ohms results in 320 ohms. Across a 5V supply, that gives a current flow
> of only 15.6mA, which results in a total output voltage of 3.4V or so.
>
> How did you get 4.2V at 19mA? That implies an internal resistance of
> about 43 ohms or so. If that is indeed the case, then shorted one way
> or the other, the WDC part ought to draw (or give) a monsterous
> 116.25mA -- almost 3 times the amount you specified.

It's not a linear resistance, so you can't just equate it to a resistor in series with relay contacts. There's some sort of current-limiting mechanism whereby the transistor begins to shut down as you approach this level.

The numbers I got were from actually measuring (although you can bet I didn't leave it on a dead short for very long, since I didn't want to ruin the part). I took measurements with various resistances, and reported the ones that tell the most about the part's output capability.

> maybe the CMOS 65C22 requires a CMOS logic level on the data-bus.

The WDC data book says it uses the standard TTL levels.

> Also, since the 65C22 is CMOS, it requires more capacitance close
> to the chip and a better ground connection. CMOS chips draw less
> average current but are more "spiky" on their current draw and hence
> require more capacitors.

This results from the faster switching the newer CMOS parts give, not from its just being CMOS. The size of the spikes on the power and ground pins will also depend on the capacitive loading at outputs. Less capacitive loading (like 10pF instead of 100) will reduce the spike.

This does bring up a good point though. If an LS-type output is driving two types of inputs at the same time, one being TTL and the other 74HC or 74AC, the loading that the TTL-type input (or a few LSTTL-type inputs) puts on the LSTTL output may keep the logic-1 voltage from rising high enough for the 74HC or 74AC to see it as a valid 1. For that situation, you can use 74HCT or 74ACT (the T meaning that the input thresholds are made to be completely compatible with TTL), or, better yet, replace the bipolar logic with CMOS. If you only have CMOS loads on a TTL or LSTTL output, that output will be able to pull up to at least 3.5 or 4V, so there's no problem.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


Last edited by GARTHWILSON on Tue Jan 30, 2007 8:40 pm, edited 1 time in total.

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PostPosted: Sun Oct 12, 2003 1:18 am 
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Hi 8Bit,

I think that I can nail this problem down for you if you list all the components (specific logic types) in the circuit (including any pull-ups). Just include a simple narrative about how they are connected.
For example, the CPU has one SRAM one EPROM and a PIO on the
data bus. The PIO is connected to a blah, blah, blah. You get the idea.


Thanks,
Bye,

Paul


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PostPosted: Mon Oct 13, 2003 6:40 pm 
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Paul,

Thanks for helping. The video circuit is using my stock sbc-2 v2.3 board with the VIA connected to my phase two video test circuit. Both schematics are on my web site (link below). Port A is the data bus and port B is the control bus. The 74LS373's are used to latch data from port A to supply RAM/EEPROM addresses. This is all on a solderless breadboard. Amost all of the IC's have a .01uF bypass cap installed.

The EEPROM programmer has two 74LS373 8-bit latches with the D side connected to VIA port A. The Q side is connected to the address pins of the 28256 32k EEPROM. Port A is also connected to the data bus of the EEPROM. Port B has pins connected to the 74LS373's EN pins and also to the /CS, /OE, and /WR pins of the EEPROM. I am not using any bus pull-up resistors. This circuit is socketed and soldered using kynar insulated wire for point-to-point wiring. There are no bypass caps on the board.

Any help would be greatly appreciated.

http://65c02.tripod.com/

Follow "hardware" link to sbc2 v2.3 and "IO devices" link for the video test circuit.

Thanks!!!!

Daryl


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PostPosted: Tue Oct 14, 2003 3:20 am 
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Hi 8BIT,

Try a CMOS EEPROM.
You are asking the EEPROM which is TTL to drive the CMOS inputs
of the 65C22.

Also, make sure that after you give a read command to the EEPROM,
give a pause in your code before you read the data from port A.

If I had the circuit in front of me, I would try and determine whether the
reads or write are failing. (chances are only one is). Ask yourself this
question "which is failing, reads or writes?" So, write a known pattern
to the EEPROM and read it back using the 6522. Or write it with a known
pattern with the 6522, and then read it back with the 65C22.

Once you determine the failing case, try and get it to fail reading/writing
in a loop and put a scope on it.

You might need pull-ups on the data bus (6502 side). Some SRAM's spit
out TTL level even though they are CMOS parts. This was done during
the golden age of computing because CMOS RAM went into NMOS circuits
when they were first introduced. CMOS CPU's came much later. This trips-up a lot of designers.

Please let me know what happens.

Thanks,
bye,

Paul


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PostPosted: Wed Oct 15, 2003 12:46 pm 
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I've had some progress and some setbacks.

Upon further study, I realized that my EEPROMS and the SRAM were CMOS devices. So, I changed the 74LS373's to 74AC573's (same device, different pinout). I noticed much better performance right away.
(Thanks Garth for the suggestion!)

The setback comes with the 74ACT715. It keeps reseting itself, which disables its clocks and the display. I'm sure its noise of some sort. I'll track it down.

Guess I'd better go back and read up on TTL, LSTTL, and CMOS device connections.

Thanks to all for the suggestions and help!

Daryl


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PostPosted: Wed Oct 15, 2003 8:04 pm 
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Fairchild's applications note 319 at https://web.archive.org/web/20161223140 ... AN-319.pdf compares the LS and HC logic families.
Ap. note 368 at https://web.archive.org/web/20181110040 ... AN-368.pdf discusses HCT and TTL.
AN375 at https://web.archive.org/web/20170808194 ... AN-375.pdf and AN377 at https://web.archive.org/web/20140801155 ... AN-377.pdf may be helpful in matters of noise at the inputs and I/O levels.
AN314 at https://web.archive.org/web/20161223134 ... AN-314.pdf also addresses interfacing between TTL and CMOS.

AN640 at https://www.onsemi.com/pub/Collateral/AN-640.pdf.pdf is a good one for understanding ground bounce and decoupling.
AN680 at https://www.onsemi.com/pub/Collateral/AN-680-D.PDF addresses dynamic thresholds and noise margins, which ground bounce is involved in.
AN393 at https://www.onsemi.com/pub/Collateral/AN-393-D.PDF deals with transmission-line effects. The newbie may think ground is ground is ground, and you may not intentionally have any RF transmission lines; but if you build with fast logic on a big layout with long wires especially with no ground plane, this stuff can bite you. 20 or 25 years ago some people in the electronics field went into digital thinking it would be simpler mathwise and they'd avoid some of the analog complications. But as digital got faster, it gradually turned into the worst form of analog-- RF!

True, it will take some time to read through this stuff, and some of this material will be too technical for some readers. It's not necessary to understand every little bit of it; but understanding the principles behind what's going on here will save you a lot of time and help you advance. And there's more where that came from. https://web.archive.org/web/20120907062 ... am_d5.html has a guide to Fairchild's ap. notes.

Garth

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


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