I am having trouble interfacing my VIA's IO ports to latches. I have Port A wired as a data bus, feed two 74LS373's and one 28256 EEPROM's data port (a simple EEPROM programmer).

The 74LS373's latch high and low address bytes, which are output to the EEPROM address pins. Port B is used to latch the 74LS373 and control the EEPROM's /CE, /OE, and /WE pins.

When I run with a MOS 6522 @ 2MHz, everything works great. When I change to a new WDC65C22, I get random errors. I tried it at 1MHz and at 4MHz with the same results. I've tried to insert NOP's all over the code to ensure enough time between control line changes with no change.

In my code, I disable the EEPROM, set an address on PORT A, and toggle the bit on Port B that controls the 74LS373 latch. Do the same for the other latch, and then enable the EEPROM. I can then either read or write to it. What happens is that some bytes (random) do not program properly. I am following the proper programming procedures, as evidenced by the MOS 6522 working.

Now, I use a very similar setup on my video test circuit and am getting the same indications there. The MOS 6522 will refresh the display perfectly every time. The WDC part gets random bytes that are not properly written.

I'm think its a hardware issue. Either too many LS parts connected to Port A or something along that line. Also, could writing to Port B cause noise during the transition. I am only changing one bit at a time, but could other bits be pulsing?

Does anyone have any suggestions? Unfortunately, all I have for test equipment is a simple logic probe and a DVM.

Thanks!

Daryl

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What's an additional VIA among friends, anyhow?

I read in the 6522 article by Bill Mensch (located on this site) that all I/O pins on the 65C22 use the same basic buffer design. Consequently, the I/O pins are also totem-pole, whereas the Rockwell unit is open-drain.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Based on what you wrote, I calculated the impedance (for lack of better word) to be 100 ohms for the WDC part. So adding 220 ohms to 100 ohms results in 320 ohms. Across a 5V supply, that gives a current flow of only 15.6mA, which results in a total output voltage of 3.4V or so.

How did you get 4.2V at 19mA? That implies an internal resistance of about 43 ohms or so. If that is indeed the case, then shorted one way or the other, the WDC part ought to draw (or give) a monsterous 116.25mA -- almost 3 times the amount you specified.

Hi 8Bit,

What CPU are you using?

If it's an NMOS 6502, maybe the CMOS 65C22 requires a CMOS
logic level on the data-bus. If so, you could try adding pull-ups
to the data-bus or switch to a 65C02 CPU.

Also, since the 65C22 is CMOS, it requires more capacitance close
to the chip and a better ground connection. CMOS chips draw less
average current but are more "spiky" on their current draw and hence
require more capacitors.

Hope this helps.

Bye,

Paul

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Hi 8Bit,

I think that I can nail this problem down for you if you list all the components (specific logic types) in the circuit (including any pull-ups). Just include a simple narrative about how they are connected.
For example, the CPU has one SRAM one EPROM and a PIO on the
data bus. The PIO is connected to a blah, blah, blah. You get the idea.


Thanks,
Bye,

Paul

Paul,

Thanks for helping. The video circuit is using my stock sbc-2 v2.3 board with the VIA connected to my phase two video test circuit. Both schematics are on my web site (link below). Port A is the data bus and port B is the control bus. The 74LS373's are used to latch data from port A to supply RAM/EEPROM addresses. This is all on a solderless breadboard. Amost all of the IC's have a .01uF bypass cap installed.

The EEPROM programmer has two 74LS373 8-bit latches with the D side connected to VIA port A. The Q side is connected to the address pins of the 28256 32k EEPROM. Port A is also connected to the data bus of the EEPROM. Port B has pins connected to the 74LS373's EN pins and also to the /CS, /OE, and /WR pins of the EEPROM. I am not using any bus pull-up resistors. This circuit is socketed and soldered using kynar insulated wire for point-to-point wiring. There are no bypass caps on the board.

Any help would be greatly appreciated.

http://65c02.tripod.com/

Follow "hardware" link to sbc2 v2.3 and "IO devices" link for the video test circuit.

Thanks!!!!

Daryl

Hi 8BIT,

Try a CMOS EEPROM.
You are asking the EEPROM which is TTL to drive the CMOS inputs
of the 65C22.

Also, make sure that after you give a read command to the EEPROM,
give a pause in your code before you read the data from port A.

If I had the circuit in front of me, I would try and determine whether the
reads or write are failing. (chances are only one is). Ask yourself this
question "which is failing, reads or writes?" So, write a known pattern
to the EEPROM and read it back using the 6522. Or write it with a known
pattern with the 6522, and then read it back with the 65C22.

Once you determine the failing case, try and get it to fail reading/writing
in a loop and put a scope on it.

You might need pull-ups on the data bus (6502 side). Some SRAM's spit
out TTL level even though they are CMOS parts. This was done during
the golden age of computing because CMOS RAM went into NMOS circuits
when they were first introduced. CMOS CPU's came much later. This trips-up a lot of designers.

Please let me know what happens.

Thanks,
bye,

Paul

I've had some progress and some setbacks.

Upon further study, I realized that my EEPROMS and the SRAM were CMOS devices. So, I changed the 74LS373's to 74AC573's (same device, different pinout). I noticed much better performance right away.
(Thanks Garth for the suggestion!)

The setback comes with the 74ACT715. It keeps reseting itself, which disables its clocks and the display. I'm sure its noise of some sort. I'll track it down.

Guess I'd better go back and read up on TTL, LSTTL, and CMOS device connections.

Thanks to all for the suggestions and help!

Daryl

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?