I have a simple question about the capacitor between VCC and GND in relation to the 6502.

Should it link VCC to all the GND pins, or is one enough?

I realize this sounds a little silly, since GND is a common connection - but the file I looked at said 'as close as possible to the mchip'. Since the 6502 has GND pins at opposite ends of the chip, and my GND circuit runs around the edge of the board, should I run a second capacitor for the pin21 GND? or is one enough?

First the long answer-- (Why do I always get carried away at the keyboard?)

If you're only running a 1MHz 6502 and a couple of similarly slow peripheral ICs, you can get away with some pretty sloppy construction and it'll still work. However until you've worked in some kind of engineering at the higher frequencies, it's hard to grasp just how much stray inductance and capacitance your connections have, and how severely they can hamper operations when you do drop some faster parts in and turn up the clock speed.

Even in our electronics for private aircraft, I comonly get an installer calling from a hangar somewhere having a devil of a time with noise getting into our system, and it virtually always turns out that they thought ground is ground is ground, and their ground scheme is all messed up. The fact is that any length of conductor, even wing spars and large aluminum aircraft fuselage structural members do not have zero ohms impedance between two places. If a current is passed through this non-0 impedance, you develop a voltage across it, which could end up referencing an input against a noise signal instead of a quiet ground.

One result of the same concept in a digital circuit board is ground bounce. To make a silly but perhaps easier-to-understand analogy, imagine lying on an air mattress in a calm swimming pool, and then someone jumps in and you suddenly find yourself bobbing up and down. An IC's output which should be at a steady state does this when it is referenced against a ground that is going up and down as a result of other outputs changing the load on the ground connections. The supposedly steady-state output can easily go up and down enough to change states, and even repeatedly trigger a flip-flop or something that shouldn't be getting triggered at the time. When you see it on the oscilloscope, you will see that the ringing takes time to die out. If the clock speed is fast enough that there's not time for the ringing to die out before you're into the critical set-up time, what is the processor, memory, or other IC input supposed to latch onto? You'll have reliability problems which will probably turn the whole thing non-operational.

For a good discusson on ground bounce, see Fairchild's applications note AN-640 at http://www.fairchildsemi.com/an/AN/AN-640.pdf If it seems all too theoretical, at least look at the design rules near the end to keep the problems from turning all too real. Another ap. note on design considerations, including decoupling requirements is AN-520 at http://www.fairchildsemi.com/ms/MS/MS-520.pdf . If you still haven't had enough math and graphs and so on, see AN-340 on transmission-line effects at http://www.fairchildsemi.com/an/AN/AN-340.pdf . If you have even a small grasp on these concepts, you can make some really first-rate home computer designs.

Now if you really want the short answer, use a small board with parts close together so the connections are no longer than necessary, and do put a .01uF from power to ground at each IC, keeping the connections to the IC's power and ground pins just as short as possible. Bigger capacitors are not usually better. In fact with the lead inductance, a .1uF capacitor may actually turn inductive at only 15MHz which is almost a low enough frequency to start ruining a 1MHz square wave. With the same lead length and orientation relative to other wires and things on the board, the .01uF capacitor will move that resonance up to about 50MHz. Ideally you'd have power and ground planes; but next-best would probably be to have kind of a star arrangement so all the power and ground connections go to a central power distribution point on the board, in addition to daisy-chaining them.

It wouldn't hurt to put a second capacitor to your other uP power pin, but the WDC 65c02 in a DIP only has ground on pin 21, while pin 1 is the VP\ (vector pull) output. The other packages, PLCC and PQFP, have extra power and ground pins, and in addition, the connections from the board to the die (the actual chip inside the IC) are shorter due to the smaller packages, so they're better suited for higher speeds.

Garth

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http://WilsonMinesCo.com/ lots of 6502 resources

Hey Garth.. feel like doing some mathematics??

You got me interested in the decoupling capacitance (mainly because I want to do it right). I read over the Fairchild document, and their formula is kinda confusing. Would you mind checking my working....

6502 (commodore data sheet)
max current draw - 160mA
rise/fall time - 10ns
vdd droop - <250mV (from the 5V +- 5% = 250mV)

gives a capacitance of 0.0064uF

The WD65c02 is lower still due to its lower max current.

Is this in some way related to your advice of using a 0.01uF for the decoupler?

It seems to make sense to me at the moment (although it is 3am), but I want to make sure I get it right so I can do it properly on other chips as well. Is there any harm in going too large?

Your .006uF is sure close to .01uF; but if you're looking at the equation I think you are on page 12 of MS-520, the current is not the overall DC draw (remember NMOS takes a lot of current even when not switching), but the current to charge up the load capacitances at the time of switching. This might take a little more time to figure out from things like the number of CMOS input loads the various pins will be driving. In the case of the ap. note, they were talking about driving a controlled-impedance bus, a little bit simpler situation for this calculation. Now understanding the potential problem and what causes it, if you want to get really detailed you could add up the capacitive loads from the data sheets of the parts in your design, calculate things like inductances of pins and traces or wire-wrap wires, and come up with optimized capacitances.

If you don't want to go to that extent, you can just take advantage of others' experience and just put a .01uF across each IC with leads as short as possible and call it done. It will still get you in the ballpark. The understanding will keep you from making common mistakes and maybe some not-so-common ones too. We call it "good engineering practice," a nebulous term that is even used in some government documents, referring to going on experience and related knowledge to do what you think is best when it's not possible to fully model all the invisible elements of a circuit for analysis.

I feel like the more I write, the less I'm saying, so I'll shut up now. Hopefully this helped at least a tiny bit.

Please don't ever shut up Garth

Even when you think you've said nothing, I still find something interesting in it.

I've only been on the site a week now, and you're turning into my local 6502 guru Hope you don't mind