Hi guys

Just a quite basic question about timing.
Today, Ben Eater released a video which is effectively doing the same thing as me: implementing a universal timing (or tick) system. His system runs at 1MHz and uses T1 timer in continuous running mode and increment memory everytime T1 hits 0 using ISR.

Question: My system interrupts at 1ms intervals & writes to RAM each time, much like Ben's does. Is this too often load-wise, or should I pad it out to 2 or 3ms? I can't go beyond 3ms due to the constraints of allowing up to 20MHz MPU and the limit of 16bits for the T1 counter. Is there a better way of doing this (short of using a RTC)?

Here are my calculations (please let me know if they don't make sense):

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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Sorry for the (very) late response! I just realised that I didn't reply.
Thanks for advising, Garth.
I ended up settling on 5ms as 1ms seemed just too often and the more I/O I add, the greater the overhead per interrupt.
Also, good to know about the cycle adjustment re the auto-reload .

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What clock speed are you using with that? I might modify mine as I really don't need it to be too often and my in-progress upcoming 65816 design I may ditch it entirely as I'm incorporating a timer IC, although I'll have to clock stretch on access as it's 70ns.

[Edit] I assume you have a lower PHI2 as otherwise the number exceeds two bytes (unless you tick the memory every two interrupts)?

For mine:


CyclesPerMS = 12 * 1,000 = 12,000
SystemVIA_T1counter = 12,000 * 10 = 120,000
SystemVIA_T1counter = 120,000 - 2 = 119,998

LSB = 119,998 MOD 256 = $BE
MSB = 119,998 DIV 256 = $1D4 (thus too large)

So the highest speed PHI2 can go to allow 10ms is just over 6MHz.
The only solution to that would be clock stretch the PHI2 into VIA *all of the time* and try and match access to it (not really do-able) or maybe put something slower on PB6 and pulse count? Obviously beyond dropping PHI2 to 6MHz.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I left in an option to for the SC28L92 for this design, but not looked into how it's implemented beyond the pinout yet. I'll do so in a bit (I have both of your guides that you kindly post elsewhere ) and look at using it's clock.


I was really after a RTC mostly and a jiffy timer as an after thought, but it's good to know. By too fast, do you mean it was running it's internal clock faster than advertised?


The LSB (T1CL) and MSB (T1CH) of the VIA T1 clock/timer.


I fully agree. Maybe they thought that having the option on pulse counting on PB6 made up for that? Especially with the WDC designs as they probably wanted to keep backward compatibility.

As for 16MHz: my current design seems ok at that speed apart from the VIAs which fall to bits after 12MHz. Probably routing as the clock seems stable and (mostly) noiseless and the MPU/RAM/ROM all seem fine - certainly the code from the ROM runs and RAM (slowest component at 55ns) tests/stack access show fine. VIAs aren't CS tied to PHI high either, but if you up PHI2 from 14MHz to 16MHz they stop sending out interrupts. Bring PHI2 down to 14MHz (without reset) and the interrupt outputs again - as measured on the VIA. I might try swapping them out to see if it's just a bit of variability as 14MHz is the stated maximum. I did notice a bit of noise on the power rail, though, some may a bit of ensitivity to that? Got penty of bypass & main board 33uF (tants) so need ot investigate.

Just to add a data point... Not seeing any issues on my Ruby 816 boards at 16Mhz with a 1Khz interrupt...

-Gordon

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

Various things could cause this, and I'll explain one that seems worth looking into.

You're already aware, I think, that a VIA needs its Chip Select and Register Select inputs to be valid before the rise of Phi2. My concern involves the Chip Select inputs.

It may be that your glue logic (the address decoder) is the limiting factor. That is, at low clock rates the glue logic may fast enough. But above 12 MHz the rise of Phi2 happens sooner. And it could be that when Phi2 rises the VIA's Chip Select is not yet in the appropriate state.

Is the schematic for your glue logic posted anywhere? And are the chips in your project socketed? (An upgrade to 74AHC family may offer a quick fix!)

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I can definitely see the VIA being selected, but I don't know if the it's outside the acceptable window/too late.
The CPLD is an ATF1504AS 7ns part which should be fast enough. As the schematic is very large and spread out, I've posted relevant parts below.
I'll also post some of the CPLD code shortly.

Core (plus serial):



CPLD (contains all glue logic):



VIAs:

CPLD code
I've removed any irrelevant bits (RAM banking, RAM/ROM selects, etc.) for clarity:

Pin definitions:



VIA device selects:



IRQs:

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I've attached the entire PLD file here: (re-uploaded)
My snippets in the previous post had the IOSEL is seto BaseAddr of 90xx-99xx which is incorrect - I was playing around with the address ranges previously, testing with WinCUPL sim and hadn't restored the values. I've now restored it to 90xx-9Fxx. Not that it makes any difference to the VIAs.

I think we previously discussed this setup in another thread/PM, but for anyone else:

- iosel is set to true if:
A8..A15 (in the code it's referred to as A0..7) of the address bus is $9xxx: $90 through to $9F (so the MPU address bus is $90xx to $9Fxx).

- The VIA chip selects (dev_via1_sel & dev_via2_sel) are true if:
For VIA 1: iosl AND'd to the lower MSB address nibble (A8 to A11) equaling %0001 (i.e. 1) is true. So the address is $9xxx from iosel and $x1xx here must be: $91xx
For VIA 2: iosl AND'd to the lower MSB address nibble (A8 to A11) equaling %0010 (i.e. 2) is true. So the address is $9xxx from iosel and $x1xx here must be: $92xx

So this gives $9100 to $91FF for VIA1 and $9200 to $92FF for VIA2 (of course, each VIA only uses the LSB lower nibble : $0-$F so a bit of wastage address wise, but quite reasonable)

The pin outputs going to VIA1 and VIA2 are inverted, so 1 becomes 0 (high goes low) so the device is selected