Hi all. A most excellent effort has been shown by Bitwise and teamtempest to create an assembler for the 65Org16 CPU. In all honesty, I have not gotten around to teamtempest yet, as I am concentrating alot of my time on the hardware aspect of this project, so my time is very limited. Although BigEd has tested them both.
But IMHO, someone needed to continue
Dr. Jefyll's topic about a compiler for the 65Org16. Instead of a compiler though, how about a translator. I started a new thread here because I would like to explore the assembler Bitwise has produced in order to compare some 65Org16 code to 6502 code.
So, as a first step, I would like to check out the binary output of Bitwise's 65Org16 assembler...
We need to compare the code in .bin (binary) form after his assembler converts the boot.asm and then compare it to an original 6502 binary. This should not only point out possible errors in the draft assemblers, but also make us realize if a translator, i.e. automatic porting, is even possible. Also, the FPGA can be programmed with this binary file. I personally think it is possible, and a great many programs alot of people have put much skill and genius into can be reborn! Alas, I am thinking in general terms only ATM.
Now it's time to get to the specifics and to prove and disprove. Hopefully a most constructive argument will result!
So, I would like to start here:
BitWise wrote:
Highly experimental draft assembler and linker.
http://www.obelisk.demon.co.uk/files/65016.zip...
The binary and hex file outputs from the linker look OK but need more testing...
by critiquing this simple adding program using the 16-bit data and 32-bit address format of the 65Org16:
Code:
;==============================================================================
; Example Boot ROM for 65Org16
;------------------------------------------------------------------------------
.TITLE "65Org16 Simple Add"
.CODE
.ORG $FFFFF000
RESHandler:
CLC
LDA $00000002
ADC #$0001
STA $00000000
LDA $00000003
ADC #$0001
STA $00000001
IRQHandler:
RTI
NMIHandler:
RTI
;===============================================================================
; Vectors
;-------------------------------------------------------------------------------
.ORG $FFFFFFFA
.WORD NMIHandler
.WORD RESHandler
.WORD IRQHandler
.END
The resultant binary:
Code:
0018 00A5 0002 0069 0001 0085 0000 00A5 0003 0069 0001 0085 0001 0040 0040
Observations:
The length of the file is correct, everything is correct, except for the expected 32-bit address. You can see after the ($00A5) LDA, only a 16-bit address ($0002) is shown.
Is it optimizing the $0000 MSB value out?
YES!Making an address change to prove this:
Code:
;==============================================================================
; Example Boot ROM for 65Org16
;------------------------------------------------------------------------------
.TITLE "65Org16 Simple Add"
.CODE
.ORG $FFFFF000
RESHandler:
CLC
LDA $FFFF0002
ADC #$0001
STA $FFFF0000
LDA $FFFF0003
ADC #$0001
STA $FFFF0001
IRQHandler:
RTI
NMIHandler:
RTI
;===============================================================================
; Vectors
;-------------------------------------------------------------------------------
.ORG $FFFFFFFA
.WORD NMIHandler
.WORD RESHandler
.WORD IRQHandler
.END
The resultant binary:
Code:
0018 00AD 0002 FFFF 0069 0001 008D 0000 FFFF 00AD 0003 FFFF 0069 0001 008D 0001 FFFF 0040 0040
I'm starting to get a good feeling about this. Hopefully it's not just a lack of sleep...
EDIT: Fixed a bad link.
EDIT: Renamed Title
EDIT: Fixed mispelling