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PostPosted: Sun Aug 14, 2011 4:01 pm 
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The issue of an assembler for the fledgeling 65Org16 project has been successfully dealt with in this thread, but in future a C compiler may become a priority. Today I stumbled across some material that instantly made me think of the 65Org16.

Buried in a corner of Bill Buzbee's wonderful homebrewcpu.com site he explains how he retargeted LCC for "a 16-bit accumulator machine [which] addresses memory as an array of 16-bit words." The remarks are at the very bottom of this page.

Although I'm no compiler expert myself, and although there's not yet any need for a compiler for the 65Org16 project, I thought it might be helpful to post Bill's comments as the seed for an eventual discussion.

-- Jeff


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PostPosted: Tue Aug 16, 2011 2:46 am 
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Interesting. I see that not only did he run across a number of the same issues we did (particularly the "hard-coded eight-bits-in-a-byte" assumption), he also uses terms in the same way we began to (eg., "a 'byte' is the minimum addressable unit").


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PostPosted: Tue Aug 16, 2011 4:29 am 
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Very handy link - many thanks!
Ed


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PostPosted: Tue Aug 16, 2011 8:17 am 
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That guy is a genius! Very interesting stuff and it sorta got me back to re-thinking of something that I would like to get done eventually.

It's a 6502 program that could translate a target program, written in 6502 assembly, into 65Org16...
Before I go on and make a total fool of myself, is this what Bitwise and Teamtempest have already done? or have they successfully made a 65Org16 assembler?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502


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PostPosted: Tue Aug 16, 2011 9:41 am 
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ElEctric_EyE wrote:
That guy is a genius! Very interesting stuff and it sorta got me back to re-thinking of something that I would like to get done eventually.

It's a 6502 program that could translate a target program, written in 6502 assembly, into 65Org16...
Before I go on and make a total fool of myself, is this what Bitwise and Teamtempest have already done? or have they successfully made a 65Org16 assembler?

My assembler translates directly to 65Org16 opcodes. I had to make a number of changes to remove 8-bit thinking in the original source.

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Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs


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PostPosted: Tue Aug 16, 2011 11:48 am 
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Ah yes. I thought I already had Java, but I installed it and I've got yours working now. Thanks for doing that! I see it is an assembler... Will try Teamtempest assembler to be fair. I know he is on 56K modem, and not always online...

How hard do you think it would be to get a 4K .bin file that conatins a 8-bit 6502 program, and automatically translate it to 65Org16?
I was thinking about it, and at least one rule would have to be followed: The 8-bit program to be translated would have to start out with an opcode, i.e no data values at the very beginning. So the translater can track the opcode conversion...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502


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PostPosted: Tue Aug 16, 2011 2:41 pm 
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ElEctric_EyE wrote:
Ah yes. I thought I already had Java, but I installed it and I've got yours working now. Thanks for doing that! I see it is an assembler... Will try Teamtempest assembler to be fair. I know he is on 56K modem, and not always online...

How hard do you think it would be to get a 4K .bin file that conatins a 8-bit 6502 program, and automatically translate it to 65Org16?
I was thinking about it, and at least one rule would have to be followed: The 8-bit program to be translated would have to start out with an opcode, i.e no data values at the very beginning. So the translater can track the opcode conversion...

I don't think it would work. For example consider a simple code sequence like:
Code:
  CLC
  LDA A+0
  ADC B+0
  STA C+0
  LDA A+1
  ADC B+1
  STA C+1

If you convert this code to 65Org16 it won't work as expected. Rather than being a 16-bit addition it would become a 64-bit addition. All such sequence would have to be rewritten to yield the expected runtime behaviour.

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Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs


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PostPosted: Tue Aug 16, 2011 4:59 pm 
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Well for it to work, all 8-bit opcodes and all 8-bit operands would be shifted right 4 times in the 8 to 16-bit translation process. Just thinking out loud... Lemme try and use your assembler to see if it'll work using your example above...

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PostPosted: Tue Aug 16, 2011 5:18 pm 
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I get an error. The file is called ADD.asm. I type in NMAKE ADD.asm. What am I doing wrong? Maybe I should start a new thread?...

Code:
;==============================================================================
; Example Boot ROM for 65Org16
;------------------------------------------------------------------------------

      .TITLE   "65Org16 Simple Add"

      .CODE
      .ORG   $FFFFF000
      
RESHandler:      
      CLC
      LDA $00000002
      ADC #$0001
      STA $00000000
      LDA $00000003
      ADC #$0001
      STA $00000001
A:      JMP A

      
IRQHandler:
      RTI

NMIHandler:
      RTI
      
;===============================================================================
; Vectors
;-------------------------------------------------------------------------------
      
      .ORG   $FFFFFFFA
      
      .WORD   NMIHandler
      .WORD   RESHandler
      .WORD   IRQHandler
      
      .END

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65Org16:https://github.com/ElEctric-EyE/verilog-6502


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PostPosted: Tue Aug 16, 2011 8:32 pm 
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I believe it should be relatively easy to create CPU and Platform files for Atalan to support 650org16.

Atalan compiler supports defining processors in code and integer types are defined using intervals - so no particular byte size is expected.

Although it's not going to be that easy, we can start by redefining byte to be 0..65535 in the m6502.atl definition:

Code:

;ATALAN definitions for 6502 CPU

type
   byte:0..255
   card:0..65535
   int:-32768..32767
   long:0..$ffffff
   sbyte:-128..127
   byte1:byte() or sbyte()
   byte2:card() or int()
   byte2a:byte2 or adr
   byte1arr:array(card) of byte1
   _byte1arr2D:array(card,card) of byte1

;==============================
;Definition of type allocations
;==============================

;rule alloc %A:0..255  = ".ds 1"

rule alloc %A:struct(), %B                         = "   .ds %B"
rule alloc %A:array(card) of byte1, %B            = "   .ds %B"
rule alloc %A:array(byte) of card, %B            = "%A_lo:" "   .ds %B" "%A_hi:" "   .ds %B"
rule alloc %A:array(byte,byte) of byte1, %B, %C   = "   .ds %B*%C"
rule alloc %A:byte                               = "   .ds 1"
rule alloc %A:card                               = "   .ds 2"
rule alloc %A:long                               = "   .ds 3"
rule alloc %A:adr                                = "   .ds 2"
rule alloc %A:-128..127                          = "   .ds 1"
rule alloc %A:int                                = "   .ds 2"

;Define cpu registers.
;Any variable defined in cpu scope is considered a register.

CPU:scope =
   a:0..255
   x,y:0..255
   c,z,v,n:0..1   
   ac@(a,c)
   azn@(a,z,n)
   aczn@(a,c,z,n)
   xzn@(x,z,n)
   yzn@(y,z,n)
   as@(a,c,z,n,v)   ; this is set of flags used for result of adc, sbc
   cznv@(c,z,n,v)
   czn@(c,z,n)
   in void:0..255  ;This is special variable used to implement touch instructions.
   zn@(z,n)
   xy@(x,y)
      
   ;Definition of the more common 6502 instructions as macros, so the code is more readable
   lda:macro o = instr let a, o
   ldx:macro o = instr let x, o
   ldy:macro o = instr let y, o
   sta:macro o = instr let o, a
   stx:macro o = instr let o, x
   sty:macro o = instr let o, y

   clc:macro = instr let c, 0
   sec:macro = instr let c, 1   

   adc:macro o = instr add as, ac, o
   sbc:macro o = instr sub as, ac, o
   inx:macro = instr add xzn, x, 1
   iny:macro = instr add yzn,y,1
   dex:macro = instr sub xzn,x,1
   dey:macro = instr sub yzn,y,1
   inc:macro o = instr add (o,zn), o, 1
   dec:macro o = instr sub (o,zn), o, 1

   lsr:macro (o=a) = instr div (o,czn), o, 2 
   asl:macro (o=a) = instr mul (o,czn), o, 2 
   ror:macro (o=a) = instr rotr (o,czn), (o,c), 1 
   rol:macro (o=a) = instr rotl (o,czn), (o,c), 1 


I would gladly help anyone who would like to try.
Is there some emulator for 65org16?


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PostPosted: Tue Aug 16, 2011 8:40 pm 
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Sounds promising!

There's no emulator... I had a quick look yesterday at Mike's py65 and I don't think it should be too hard to port. I intended to start the job but got sidetracked. (My other favourite is run6502 which is smaller and faster but less friendly (no monitor) - I haven't looked at that. It uses an array to map memory which would be rather large for this machine.)


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PostPosted: Tue Aug 16, 2011 9:34 pm 
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ElEctric_EyE wrote:
I get an error. The file is called ADD.asm. I type in NMAKE ADD.asm. What am I doing wrong?
The Makefile only knows how to build from boot.asm: run NMAKE and it will run commands like these
Code:
java -cp ./65016.jar org.x6502.x65016.As65016  boot.asm
java -cp ./65016.jar org.x6502.x65016.Lk65016 -bss $00010000-$EFFFFFFF -code $FFFFF000-$FFFFFFFF -s19 -output boot.s19 boot.obj
java -cp ./65016.jar org.x6502.x65016.Lk65016 -bss $00010000-$EFFFFFFF -code $FFFFF000-$FFFFFFFF -hex -output boot.hex boot.obj
java -cp ./65016.jar org.x6502.x65016.Lk65016 -bss $00010000-$EFFFFFFF -code $FFFFF000-$FFFFFFFF -bin -output boot.bin boot.obj
so you could modify those, or modify the Makefile. Can I suggest you write up in a new thread though?

(Edit: thanks - new thread appeared here)

Cheers
Ed


Last edited by BigEd on Wed Aug 17, 2011 4:49 am, edited 1 time in total.

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PostPosted: Wed Aug 17, 2011 2:29 am 
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ElEctric_EyE wrote:
Ah yes. I thought I already had Java, but I installed it and I've got yours working now. Thanks for doing that! I see it is an assembler... Will try Teamtempest assembler to be fair. I know he is on 56K modem, and not always online....


Okay, not always online but at least I've moved past the 56K modem era (even if the HXA website hasn't!).

HXA doesn't support the 65Org16 natively as yet. What it does do is use the HXA_T variant and an include file that implements the 65Org16 instruction set as macros (in fact it is the same file that implements the 6502 instruction set as macros, but with a different cpu definition that makes all the difference).

My thinking is that instructions-as-macros should make it easy to play around with instruction set extensions. When a complete list is settled on, then I'll create a native version.

BTW, I want that list to include at least "BSR" and "BRA". I don't care if "BSR" takes an extra cycle compared to "JSR", what I like is easy relocatability.

Like BitWise I had to re-think 8-bit assumptions I'd made.


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PostPosted: Thu Aug 18, 2011 5:54 am 
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teamtempest wrote:
My thinking is that instructions-as-macros should make it easy to play around with instruction set extensions. When a complete list is settled on, then I'll create a native version.

BTW, I want that list to include at least "BSR" and "BRA". I don't care if "BSR" takes an extra cycle compared to "JSR", what I like is easy relocatability.


I'm happy with those two - I've started a new thread to outline my thoughts.

Cheers
Ed


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 Post subject: Atalan for 65Org16
PostPosted: Sun Aug 28, 2011 7:41 pm 
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rudla.kudla wrote:
I believe it should be relatively easy to create CPU and Platform files for Atalan to support 650org16.

...

I would gladly help anyone who would like to try.
Is there some emulator for 65org16?


Yes, there is now!

It would be very interesting to see how you get on generating code for this machine... I could help... except I see that you'd prefer to help me!

(Although we have an emulator, which has a primitive assembler and disassembler and can set and show the machine state, there is not presently any breakpoint or watchpoint or tracing. There is single-stepping. Anyone with python skills could very usefully help here: they'd be helping all the CPUs which py65 supports.)

Cheers
Ed


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