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POC V1.3 runs with a 16 MHz Ø2 clock. However, the time base for jiffy IRQs is the counter/timer (C/T) in DUART #1, not the Ø2 clock generator. The C/T gets its time base from the 3.6864 MHz oscillator that runs the DUART. Hence the jiffy IRQ rate is unaffected by changes to Ø2.
I left in an option to for the SC28L92 for this design, but not looked into how it's implemented beyond the pinout yet. I'll do so in a bit (I have both of your guides that you kindly post elsewhere
) and look at using it's clock.
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Early on when I was considering the design of POC V1.0, I contemplated using a PIT of some sort. Since I was also going to incorporate an RTC (the Maxim DS1511Y), which could generate “evenly-spaced interrupts,” I went that route—until I discovered the “evenly-spaced interrupts”
came a little too fast. It was at that point that I started using the DUART's C/T, which underflows at 10 millisecond intervals. The stability of that time base is as good as the oscillator that clocks the DUART.
I was really after a RTC mostly and a jiffy timer as an after thought, but it's good to know. By too fast, do you mean it was running it's internal clock faster than advertised?
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Two bytes? To what are you referring?
The LSB (T1CL) and MSB (T1CH) of the VIA T1 clock/timer.
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I've never considered the VIA (and Commodore's 6526) to be a good source for a jiffy IRQ. That the timers are slaved to Ø2 (assuming that's what you're using as a time base) means you can't change Ø2 and expect accurate timekeeping.
...
That seems to be an awkward way to make up for a fundamental limitation of the 6522.
I fully agree. Maybe they thought that having the option on pulse counting on PB6 made up for that? Especially with the WDC designs as they probably wanted to keep backward compatibility.
As for 16MHz: my current design seems ok at that speed apart from the VIAs which fall to bits after 12MHz. Probably routing as the clock seems stable and (mostly) noiseless and the MPU/RAM/ROM all seem fine - certainly the code from the ROM runs and RAM (slowest component at 55ns) tests/stack access show fine. VIAs aren't CS tied to PHI high either, but if you up PHI2 from 14MHz to 16MHz they stop sending out interrupts. Bring PHI2 down to 14MHz (without reset) and the interrupt outputs again - as measured on the VIA. I might try swapping them out to see if it's just a bit of variability as 14MHz is the stated maximum. I did notice a bit of noise on the power rail, though, some may a bit of ensitivity to that? Got penty of bypass & main board 33uF (tants) so need ot investigate.