jds wrote:
Code:
ABORTB - tie high
A0-A15 - no change
BE - tie high
D0-D7 - no change (but consider bus timing)
E - unused
IRQB - no change
MLB - unused
MX - unused
NMIB - no change
PHI2 - use as PHI0 in was used before
RWB - no change
RDY - tie high
RESB - no change
VDA,VPA - use in address decode, see later
VDD, VSS - no change
VBP - not used
So mainly just a few pins that need pullup resistors (not sure what value is best here?) and some changes to the address decode.
I recommend that any 65C816 input that you are not immediately planning to use be pulled up through a 3.3K resistor. Doing so will give you the option of later using that input if desired. Note that if RDY is wired directly to Vcc (VDD) the WAI instruction will not have any apparent effect and if executed (intentionally or otherwise), will cause RDY to attempt to sink Vcc, with currently unknown effects.
Quote:
Code:
NEW_RAMCSB = RAMCSB & VDA
NEW_ROMCSB = ROMCSB & VPA
and I guess I/O would be treated like RAM.
The logic for RAM and ROM would be:
Code:
VDA || VPA
where
|| is logical OR.
For I/O, you can use:
Code:
VDA && !VPA
where
&& is logical AND and
! is logical NOT. If the expression
VDA && VPA is true the '816 is fetching an opcode. The
VDA && !VPA qualification would prevent I/O from being read as a source of machine instructions and is optional. If you don't care about that, the RAM/ROM qualification logic is fine.
Quote:
Now I just need to check the bus timing as well. The data bus isn't valid until the second half of the cycle. This is no problem for reads, but for writes it could be. My RAMCSB line is already qualified on PHI2 being high, so I guess that is covered too.
Chip selects should not be qualified by Ø2, especially any 65xx peripheral device (e.g., 65C22), as the address bus becomes valid midway through Ø2 low, which is indicated by VDA and/or VPA going true. What should be qualified by Ø2 is RWB, since as you noted, D0-D7 doesn't contain data during Ø2 low—in the case of the '816,it holds the bank address or undefined content. Again, the exception is with 65xx peripheral devices, on which RWB, as well as chip selects, must be valid prior to the rise of Ø2—they will not respond if not selected prior to the rise of Ø2.
Regarding Ed's comment stating that use of
VDA and
VPA is unnecessary, his opinion is contrary to the 65C816 data sheet (see sections 2.26 on page 17, and 7.5 on page 52, as well as the caveats table on page 51). Ignoring VDA and VPA can get you into trouble, even with 65xx peripheral devices. Unlike the 65C02, which performs a spurious (and usually harmless) read of the addressed device during a R-M-W instruction prior to executing the final write, the '816 in native mode will perform a spurious write on the addressed device. This behavior can cause difficult-to-diagnose problems with peripheral devices of any type. Also, indexed addressing may produce a spurious address during instruction cycles in which
VDA || VPA is false, which may cause unintended selection of the wrong device during the instruction. Depending on the device, that too could cause obscure problems.
The hardware logic required to use VDA and VPA to qualify RAM, ROM and I/O accesses is very simple. As I usually say, ignore VDA and VPA at your own peril.