This is a continuation of the topic that started here.

6502 Verilog Replica
by Xor

Summary
A logically accurate replica of the NMOS 6502, written in Verilog HDL, and based on the transistor netlist available from Visual6502.org.

Goal
The main goal of the project is for my own personal education; I wish to explore microprocessor architectures by accurately reproducing the 6502, a landmark in computing history.

Even though this project is being developed for my own personal benefit, the code will be made freely available, so that perhaps others can reap the benefits of exploring the architecturally rich MOS 6502.


The rest of this thread will consist of my own ramblings and occasional updates on this project, since I don't have a blog or anything like that, and others showed interest in reading updates on this project. Everyone is free to make comments, suggestions, praise, scorn, non sequitur, etc.

Update 1 - Now runs on Cyclone 4 FPGA!

Well, I fixed a few bugs in the 6502 core that cropped up while running the visual6502 example. Then I copied over the starfield example from 6502asm.com and worked on getting that to run correctly. After re-doing the tcstate logic, a few random control logic fixes, and putting in the code for a few more control lines, I was able to get the starfield code running.

Having done all that, I added a video output module, proper dual-clock generation, debugging sources and probes, and got the whole thing to synthesize for my Cyclone 4 FPGA.

And then, of course, I had plenty of bugs to fix. But now I have something half-way decent on the screen:

http://www.youtube.com/watch?v=b7O7QJsaHHk

I modified the starfield example to include a VSYNC wait loop, because with a 1MHz clock it ran too fast and obviously caused tearing. I'll probably need to add a small loop that waits for a few VSYNCS, instead of just one, because, as you can see in the video, it still runs too fast.

There's still a bug or two left, but I'm happy to have something running.

I'll get around to putting the code up somewhere (github?) so any interested parties can laugh at it. Some of the code is well written and accurate to the 6502 ... other parts ... not so pretty

I should also point out that the chip, as is, can be single stepped, and all the internal registers and control signals can be dumped. Really, this is for my own good, since I need to debug the countless mistakes I made. Still, I find it cool to be able to run a replica of the 6502 and peek in on its internal organs.

Update 2 - Now with less bugs!

I've now modified the starfield code to wait until every 8th frame before updating, thus slowing it down to a more visible speed I also fixed the bug in my framebuffer->DVI module and so now everything displays as it should.

YouTube video

My next work will be to clean up the code a little bit; put in a proper memory module that can be peek'd and poke'd from my PC; get a small game running (hopefully another 6502asm example) with a controller of some kind.

The dev board has some buttons on it (DE2-115 cyclone 4 dev board). I might just use those as the "controller" for now. Sure would be nice to get my USB controller working ... but that might be a bit too difficult

How fast will the core run and how many resources does it use ?

Xor welcome! Very nice to have another Verilog professional here adding your efforts and experimenting. Although I don't know the language, I can still get by using schematics and symbols for HDL/Verilog code. However, there are others here developing Verilog cores of their own. Arlet has his 6502 core, Andre is working on his 65000 project, and RUUD his RB65... That being said, once you feel your core is complete we can add it to our list we've compiled, so you can compare and contrast, although I do use Xilinx. I see you are partial to Altera. Not sure about similarities/differences for comparison purposes. Maybe you could start a new Altera 6502 Core Comparison...

Let us know when to add your core into the mix!

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

As a side project, Garth and I are working on the 65org32 instruction set and its first implementation. I'm still in the design and experimentation phase of the project though.

It will not be binary compatible with the 6502 though (nor with the 65816). However, its internal architecture and instruction-set features will be largely informed by the 6502. The idea is that one should be able to write an assembler which accepts 6502 assembly listings as input, and spits out a 65org32 instruction stream that satisfies the functionality you'd expect. (Just as Intel had intended, and with some success I might add, with the 8080 assembly listings used to create initial ports of software for the 8086.)

Hi Xor
we have some new pages on the visual6502 wiki which might be of interest to you.

The datapath
Controlling the PC incrementer
Behaviour of opcode 8B

(I'm not terribly interested in the undefined opcodes, but investigating them is a way to understanding the implementation)

Here's an example: the logic leading up the decision to increment PC:



Cheers
Ed

Hi Xor
congratulations on getting your core working - I did see your announcement but somehow it didn't go all the way into my brain. I even replied...

also very nice to see that you have an on-chip debugging system.

I don't suppose you've tried to run one of the full-on test suites? I've collected some links on the visual6502 wiki. Once you're running at MHz speeds, it becomes feasible to run these, and I think it's a very worthwhile qualification.

Cheers
Ed

Hi Xor
there's a discussion going on elsewhere about some fine details of NMI behaviour, and I realised it would be nice to be able to refer to a slightly higher-level accurate description of the 6502.

you mentioned earlier that you might put your code up on github - any further thoughts on that?

Cheers
Ed