6502.org Forum Projects Code Documents Tools Forum
It is currently Sat Nov 23, 2024 9:47 pm

View unanswered posts | View active topics


Board index » 6502.org Users Forum » Programmable Logic

All times are UTC




Post new topic Reply to topic  Page 2 of 8
  [ 110 posts ]  Go to page Previous  1, 2, 3, 4, 5 ... 8  Next
  Print view Previous topic | Next topic 
Author Message
ElEctric_EyE
PostPosted: Fri Dec 26, 2014 1:17 am 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
Since I'm not following Xilinx' rules on their recommendations for proper power supply bypassing, I'm debating on adding power supply filtering for the 3.3VCCO/AUX for the FPGA and also the 3.3V analog for the videoDAC in the form of an inductor and 2 cap's for each supply, sort of like Analog Devices does in their Connection Note (CN0282). Can anyone give me some tips on the values to shoot for? It looks like their values aim to filter out switching noise from their switching power supply IC's (ADP2301).


Attachments:
From AD CN0282 PS.jpg
From AD CN0282 PS.jpg [ 121.31 KiB | Viewed 1213 times ]

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
GARTHWILSON
PostPosted: Fri Dec 26, 2014 1:59 am 
Offline
User avatar

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8546
Location: Southern California
L1 & L7 are necessary parts of the switching regulators, and the layout of those is very critical to get good behavior, that being especially important for the analog portions of your circuit. Are you laying out that part of the power supply though?

F1 through F7 are ferrite beads. Check out this one: http://www.mouser.com/ProductDetail/Lai ... YbBQ%3d%3d (or others in that family). How much current do they need to handle? Make sure you have ones rated for it so they don't saturate and lose their "choke" value.

Next, get the 0.1uF chip capacitors as close as possible to the power connections they go to on the chip, to get the lowest possible inductance for an AC path from that power pin or ball to the ground plane. For BGA, that will probably mean putting it on the back of the board, on the side opposite the IC (although I have not done any BGA layout to speak with any authority about how to do that). You can get those in 0402--maybe smaller (since you can get by with a WVDC of 16V or even 10V)--but I don't know if you're able to mount something that small by hand. Small is good for reducing inductance though. Take a look at this article from Dr. Howard Johnson on minimizing bypass capacitor inductance. The capacitors that are 33uF in your diagram don't have to be as close.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
Top
 Profile  
Reply with quote  
ElEctric_EyE
PostPosted: Fri Dec 26, 2014 2:25 am 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
Ah, I missed the fact that they were ferrite beads! I assumed they were typical inductors based on the inductor sign but missed the F1-F7 part numbering. Thanks for pointing that out!

I can't get a bypass cap next to each of the BGA power pads, which is why I was thinking the next best thing would be to isolate the BGA 3.3V with it's own power plane and filtering, same for the 3.3V analog section of the videoDAC.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
ElEctric_EyE
PostPosted: Fri Dec 26, 2014 5:06 am 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
Every board needs a mark...

I was bored today, so I made some imaginary gears into my design. Happy Birthday somebody, heh.


Attachments:
12-25-2014 10-49-30 PM.jpg
12-25-2014 10-49-30 PM.jpg [ 304.07 KiB | Viewed 1193 times ]

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
BigDumbDinosaur
PostPosted: Fri Dec 26, 2014 10:52 pm 
Offline
User avatar

Joined: Thu May 28, 2009 9:46 pm
Posts: 8513
Location: Midwestern USA
ElEctric_EyE wrote:
Every board needs a mark...

I was bored today, so I made some imaginary gears into my design. Happy Birthday somebody, heh.

Looks like something into which a designer could really sink his teeth. :lol:

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!
Top
 Profile  
Reply with quote  
ElEctric_EyE
PostPosted: Fri Dec 26, 2014 11:31 pm 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
BigDumbDinosaur wrote:
ElEctric_EyE wrote:
Every board needs a mark...

I was bored today, so I made some imaginary gears into my design. Happy Birthday somebody, heh.

Looks like something into which a designer could really sink his teeth. :lol:

Indeed! Board design appeals to the OCD within me, but being a disorder it starts to take a toll... My apologies. Not that I have OCD. Not diagnosed anyway.. :lol:

Some progress:
1) I've started the .ucf constraints file which assigns FPGA pins for ISE to program the FPGA.
2) Also, by moving a few pads under the FPGA, current will flow much better for the 3.3V. You can see there's more space around the vias now, none are trapped. Compare to previous pic above.


Attachments:
File comment: Updated 3.3v & 1.2v power planes
12-26-2014 6-09-57 PM.jpg
12-26-2014 6-09-57 PM.jpg [ 293.22 KiB | Viewed 1171 times ]

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
ElEctric_EyE
PostPosted: Sun Dec 28, 2014 6:53 pm 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
I believe the PVBV2a has been finalized.
All the design goals have been reached for this board layout and now I feel like $200 is a price I'm willing to pay to get this thing rolling!

I've added 2 more power planes that are filtered using a ferrite bead and a few capacitors, within the 3.3V main power plane shown at the bottom pic.
One plane is for all the FPGA VCCO/VAUX pads, I count 25. The layout provides for a 0805 ferrite bead, a 0805 cap, and 2 0603 cap's. 6 amp rating of a ferrite bead this size are more than enough, as well as 33uF for an 0803 cap. I decided on a ferrite bead with a rating of 22ohm @100MHz, based on the Analog schematic I had posted above.
The other plane is for the analog 3.3V power of the ADV7125 videoDAC. The ferrite beads and caps are all 0603 sizes as the current demand is much less.

Any critiques welcome! Thank you.


Attachments:
File comment: PCB Layout. Last chapter before order.
12-28-2014 1-28-34 PM.jpg
12-28-2014 1-28-34 PM.jpg [ 1.91 MiB | Viewed 1149 times ]
File comment: Power Plane Layer
12-28-2014 1-24-50 PM.jpg
12-28-2014 1-24-50 PM.jpg [ 247.66 KiB | Viewed 1149 times ]

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
GARTHWILSON
PostPosted: Sun Dec 28, 2014 9:25 pm 
Offline
User avatar

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8546
Location: Southern California
Quote:
Any critiques welcome! Thank you.

It appears that all parts are on the top. Is that correct? If so, I think it would be good to put the power layer on the back, so it's not between the signal layers and the ground plane. The power layer has big chainsaw cuts in it, making it unsuitable as a plane layer for any signal traces that cross the cuts. I think your ground plane is continuous though, right?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
Top
 Profile  
Reply with quote  
ElEctric_EyE
PostPosted: Sun Dec 28, 2014 11:16 pm 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
GARTHWILSON wrote:
It appears that all parts are on the top. Is that correct? ... I think your ground plane is continuous though, right?

Correct, but I can't change layer assignments. I think it's SIG-POW-GND-SIG. I'm just going to have to go forward and hope for the best.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
ElEctric_EyE
PostPosted: Mon Dec 29, 2014 8:07 pm 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
Garth, I interpreted your 'jagged' comment to mean diagonal so I tried to come up with a better layout:


Attachments:
12-29-2014 3-00-01 PM.jpg
12-29-2014 3-00-01 PM.jpg [ 1.95 MiB | Viewed 1116 times ]
File comment: Internal 3.3V main, 3.3V filtered for FPGA Vcco/aux and 3.3V filtered for videoDAC 3.3V VAA, and FPGA 1.2V planes.
12-29-2014 2-58-13 PM.jpg
12-29-2014 2-58-13 PM.jpg [ 364.65 KiB | Viewed 1116 times ]

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
ElEctric_EyE
PostPosted: Mon Dec 29, 2014 8:12 pm 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
Parts list started. Discrete components have yet to be added!
Was a challenge to find the 330MHz videoDAC part. :D


Attachments:
12-29-2014 2-53-51 PM PVBV2 Parts incomplete.jpg
12-29-2014 2-53-51 PM PVBV2 Parts incomplete.jpg [ 287.74 KiB | Viewed 1432 times ]

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
GARTHWILSON
PostPosted: Mon Dec 29, 2014 8:26 pm 
Offline
User avatar

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8546
Location: Southern California
ElEctric_EyE wrote:
Garth, I interpreted your 'jagged' comment to mean diagonal so I tried to come up with a better layout:

I'm not sure what you mean by 'jagged' unless you're referring to the term "chainsaw" which just means there are cuts (regardless of shape) in what otherwise looks like a plane layer, in this case a power plane. As long as this layer doesn't get between your signal traces and the continuous ground plane, you'll be fine. Remember that any given signal trace's return current through the plane tries to run directly under that trace, taking the shape of the trace, but that if there's a cut in the trace, the return current has to take a different path and you end up with what amounts to an inductor or a stub depending on the length and width of the cut, and it degrades signal integrity. Actually, sometimes a cut in the plane, running perpendicular to the trace, is intentionally used to print an antenna on the board, something you don't want in this case. I really have no way of evaluating the effects for the particular application, so, since you're dealing with sub-nanosecond rise times for the fast, hi-res video stuff, I just shoot for next best, which we give the nebulous term "good engineering practice."

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
Top
 Profile  
Reply with quote  
ElEctric_EyE
PostPosted: Fri Jan 02, 2015 11:22 pm 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
I've finished the .ucf constraints file which assigns each pin on the FPGA a particular function for ISE to program the FPGA. This bit of work is abit mundane but it forces me to re-check pad-trace-pad IC interconnects. And I found a major problem that existed from early! Read on...
Code:
 # Spartan 6 XC6SLX25 Pin assignments on PVBV2a #  1.2.2015

 # Synchronous Ram #1 Signals #
NET "SRAddr[0]" LOC = PA4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRAddr[1]" LOC = PA3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRAddr[2]" LOC = PB3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[3]" LOC = PA2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[4]" LOC = PB2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[5]" LOC = PB1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[6]" LOC = PC6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[7]" LOC = PD6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[8]" LOC = PE7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRAddr[9]" LOC = PD8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[10]" LOC = PC8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRAddr[11]" LOC = PE8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRAddr[12]" LOC = PE10 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRAddr[13]" LOC = PA8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[14]" LOC = PB8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[15]" LOC = PA7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[16]" LOC = PC7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[17]" LOC = PA6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[18]" LOC = PB6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[19]" LOC = PA5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[20]" LOC = PB5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[0]" LOC = PC1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[1]" LOC = PC2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[2]" LOC = PD1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[3]" LOC = PD3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[4]" LOC = PE1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[5]" LOC = PE2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[6]" LOC = PC5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[7]" LOC = PE6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[8]" LOC = PD12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[9]" LOC = PC9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[10]" LOC = PA9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRD[11]" LOC = PB10 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[12]" LOC = PA10 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRD[13]" LOC = PB12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[14]" LOC = PA11 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[15]" LOC = PC11 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[16]" LOC = PC3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[17]" LOC = PE11 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRWEn" LOC = PE7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRCLK" LOC = PF1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK

 # Synchronous Ram #2 Signals #
NET "SRAddr[0]" LOC = PP4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[1]" LOC = PT4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[2]" LOC = PR5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "SRAddr[3]" LOC = PT5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //RDWR_B_VREF
NET "SRAddr[4]" LOC = PN4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[5]" LOC = PP5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "SRAddr[6]" LOC = PF3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[7]" LOC = PE3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[8]" LOC = PE4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[9]" LOC = PH1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[10]" LOC = PG3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[11]" LOC = PG1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[12]" LOC = PD5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[13]" LOC = PN1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[14]" LOC = PN3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[15]" LOC = PP1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[16]" LOC = PP2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[17]" LOC = PR1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[18]" LOC = PR2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[19]" LOC = PM3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRAddr[20]" LOC = PM5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[0]" LOC = PM4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[1]" LOC = PK6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[2]" LOC = PL5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[3]" LOC = PK3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[4]" LOC = PK5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[5]" LOC = PJ4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRD[6]" LOC = PH4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[7]" LOC = PF4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[8]" LOC = PJ1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[9]" LOC = PJ3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[10]" LOC = PK1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[11]" LOC = PK2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[12]" LOC = PL1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[13]" LOC = PL3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[14]" LOC = PM1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[15]" LOC = PM2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[16]" LOC = PL4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[17]" LOC = PH2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRWEn" LOC = PF5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRCLK" LOC = PF2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
 
  # I2C Signals #
NET "SCL" LOC = PT9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SDA" LOC = PR9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O

# RGBin Signals #
NET "Rin[0]" LOC = PK16 | IOSTANDARD = LVCMOS33;  //A0-A25
NET "Rin[1]" LOC = PK14 | IOSTANDARD = LVCMOS33;  //N_GCLK
NET "Rin[2]" LOC = PL16 | IOSTANDARD = LVCMOS33;  //FCS...LDC
NET "Rin[3]" LOC = PM15 | IOSTANDARD = LVCMOS33;  //FCS...LDC
NET "Rin[4]" LOC = PN16 | IOSTANDARD = LVCMOS33;  //A0-A25
NET "Gin[0]" LOC = PP16 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Gin[1]" LOC = PP15 | IOSTANDARD = LVCMOS33;  //FCS..LDC
NET "Gin[2]" LOC = PR16 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Gin[3]" LOC = PL13 | IOSTANDARD = LVCMOS33;  //VREF
NET "Gin[4]" LOC = PN14 | IOSTANDARD = LVCMOS33;  //A0-A25
NET "Gin[5]" LOC = PT15 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Bin[0]" LOC = PR14 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Bin[1]" LOC = PT13 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Bin[2]" LOC = PT12 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Bin[3]" LOC = PP12 | IOSTANDARD = LVCMOS33;  //A0-A25
NET "Bin[4]" LOC = PN9 | IOSTANDARD = LVCMOS33;  //A0-A25
NET "HSYNCin" LOC = PT8 | IOSTANDARD = LVCMOS33 | SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "VSYNCin" LOC = PR12 | IOSTANDARD = LVCMOS33 | SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "PCLKin" LOC = PH5 | IOSTANDARD = LVCMOS33;  //N_GCLK


# RGBout Signals #
NET "Rout[0]" LOC = PA12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "Rout[1]" LOC = PA13 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "Rout[2]" LOC = PC13 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "Rout[3]" LOC = PA14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "Rout[4]" LOC = PB14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "Gout[0]" LOC = PB16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Gout[1]" LOC = PC16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Gout[2]" LOC = PC15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Gout[3]" LOC = PD16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Gout[4]" LOC = PD14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Gout[5]" LOC = PE16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Bout[0]" LOC = PE15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Bout[1]" LOC = PF16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Bout[2]" LOC = PF15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Bout[3]" LOC = PG16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Bout[4]" LOC = PH14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "HSYNCout" LOC = PM6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "VSYNCout" LOC = PR15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "PCLKout" LOC = PJ16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK


 # Bi-Directional Communication Interface #
NET "D0" LOC = PL16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //FCS..LDC
NET "D1" LOC = PM16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //FCS..LDC
NET "D2" LOC = PN5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "D3" LOC = PT6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "D4" LOC = PN6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "D5" LOC = PP7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "D6" LOC = PT7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "D7" LOC = PH16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "CommCLK" LOC = PM7 |IOSTANDARD = LVCMOS33 //N_GCLK
NET "R_W" LOC = PR7 |IOSTANDARD = LVCMOS33 //P_GCLK
NET "PVB1RDY" LOC = PP6 |IOSTANDARD = LVCMOS33;  //USER I/O
NET "PVB1BE" LOC = PP8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK

 # Programmable Clock 1 Input from DS1085L  (Main Osc out 1 hardwired to J12)#

NET "ProCLKin1" LOC = PJ12 |IOSTANDARD = LVCMOS33;  //N_GCLK

 # Programmable Clock 2 Input from DS1085L  (Main Osc out 2 hardwired to J13)#

NET "ProCLKin2" LOC = PJ13 |IOSTANDARD = LVCMOS33;  //N_GCLK
 
 # Programmable Clock Output from K1 Controller Board #

NET "POSCin" LOC = PM9 |IOSTANDARD = LVCMOS33;  //P_GCLK

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
ElEctric_EyE
PostPosted: Fri Jan 02, 2015 11:32 pm 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
Back on Dec 13 when I posted a pic of the PCB layout, a data bus trace was left unconnected. That was the 2nd iteration of the design. I realized this error at the final 6th iteration! Quite a PITA after the board fills up and things get tight after 2 more weeks of development. Errors like this make it a real challenge to re-route so many pad-pad traces! But I did it with some sort of inner pleasure. :twisted: I've got my finger on the trigger now for EPCB production. :)


Attachments:
wiring error.jpg
wiring error.jpg [ 270.44 KiB | Viewed 1400 times ]

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
ElEctric_EyE
PostPosted: Sun Jan 04, 2015 9:54 pm 
Offline

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA
I decided to do a few schematics for a few sections of the board.

The Power Supply Section is documented, that pic is next. I'm currently working on the FPGA SPI PROMs next. Finally, the Programmable Oscillator Section. A Block diagram will finish off the visual description of this design.

Comments/critiques welcome as always! You all have been a great help spotting bungling errors.

BOM is complete:


Attachments:
1-4-2015 4-36-28 PM.jpg
1-4-2015 4-36-28 PM.jpg [ 584.23 KiB | Viewed 1380 times ]

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502
Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  Page 2 of 8
  [ 110 posts ]  Go to page Previous  1, 2, 3, 4, 5 ... 8  Next

Board index » 6502.org Users Forum » Programmable Logic

All times are UTC


Who is online

Users browsing this forum: No registered users and 7 guests

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
6502.org is an ongoing project by Mike Naberezny and contributors.