As noted previously, there's an initiative to make chips using a fully open source chip design flow, which is presently accepting submissions of open-source chip designs for free fabrication later this year.

As last year, as I understand it, they are accepting up to about 40 designs (to be selected by them if over-subscribed) and will return 50 packaged chips. I think the package is a 100 pin mini-BGA, and there are 37 I/Os available. The process is 130nm, and the I/Os are 5v tolerant. The allocation for the design is 10mm2, which is apparently up to a million gates - a great deal more than the FPGAs we deal with, although they come with onchip RAM too, so with that it might come out even. Who knows.

One interesting piece of news in this video update is that the same process is being offered commercially: 100 chips for $10k.

TBH, I think it's quite a stretch beyond an FPGA design: and having a design work on FPGA would be a pre-requisite, in practice, because for $10k you certainly want to have tested out your design. But, it's not entirely out of reach, and anyone who's got an FPGA design up and running is probably able to learn how to work their way through a chip flow.

Quick update (Edit: new location here) on the commercial offering:

$10k gets you either 100 QFN or 300 WCSP packaged parts
$20k gets you 1000 WCSP parts

So that's $20 each, for a custom chip in a tiny package with nearly 40 I/Os (5V tolerant). A pretty good deal, except for the volume: not so many retrocomputing project can hope for quantity of 1000.

One interesting possibility is to design multi-purpose chips which share I/Os between macro functions, at the cost of a few I/Os to determine which role each chip should play.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I think what BigEd is saying is that if there were a design that included a 65SPI, a hardware I2C master, a wait state generator, a couple of 6551s without the transmit bug, and a DRAM controller then you might be able to find 1,000 takers. It wouldn't be necessary to use all of the functions in a given design. Maybe in a few years time it will be $10 with a MOQ of 100.

How hobbyist friendly is WCSP? How much would a PCBA house want to put it on a DIP40 breakout board?

Indeed, that's my thinking: lots of room inside the chip, just need to use a few pins to determine function. If the chip includes some interesting or rare functions (SID...) then it might have sufficient value.

The WCSP seems to be a bare square of silicon with 100 solder bumps: very very much a surface mount device, so you need an oven (or similar) and probably a carrier board to provide a more friendly interface.

For me, this recent development shows progress in a good direction, but not yet reaching the point of being accessible enough. There was a time when FPGAs, or surface mount devices, or four-layer PCBs, were out of reach, and now they are well within reach. So it might be with custom silicon.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

The functionalities you mentioned (DRAM controller, I2C, SPI, wait state, serial port) are not very complex and can be implemented in modest 5V CPLD like ATF1508 which is $4.62 in quantity of 1 from Mouser. DRAM controller does need quite a bit of pins, so a 100-pin SMT is probably needed to do the various functions. I've implemented something like that for a Z80 SBC, ZRC. It has 2megabyte DRAM, DRAM controller, bank select logic, 6850 serial port, I2C bus, compact flash interface, driver for pixel-addressable LED (WS2812B), and importantly, a fast 64-byte bootstrap ROM. A lot of features can be packed into a small board with help of the CPLD.
Bill

Hmm, reading this more carefully it might not quite be what I'm thinking: in my picture, there's no case for "a couple of 6551s" because in my picture, each chip will be configured by tie-offs to one particular function. So, it's a multi-purpose chip in one sense, but not in another. I'm not thinking of mopping up a lot of glue or a lot of peripherals: for one reason, not enough I/Os, and for another reason, it pins down a specific idea of a system design.

Many 80s machines have some custom circuits or no-longer-available VLSI chips: those chips can presently be salvaged from existing machines, preferably broken ones, but that's not a long term answer. But all those chips have been modelled, to some degree, in projects like MAME if nowhere else. Many of them exist as open source HDL already. For some, more work is needed.

Of course there's another, different story: create a wonderful system design which needs only 36 I/Os and sell it in quantity, with some reason why an FPGA wouldn't have done the job. It's the selling in quantity which is the hurdle.

Another story again is to be happy to spend $10k on one chip just for yourself, but that's a special case!

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?