I checked Visual 6502 information. It appears to be 6502 rev D. If 6502 microprocessor is NMOS, it means that all transistors must be nMOS. If 65C02 microprocessor is CMOS, both NMOS and PMOS transistors can be combined together to become one.

I compare accumulator register between visual 6502 and schematic. The schematic looks like it has both nMOS and pMOS transistors. it is so confusing to me.

I focus SBAC with four transistors. Of course, it has six transistors including ACSB and ACDB. If register has four NANDs such as S/R latch, it should be eight transistors as schematic shows. Please clarify what are two different transistors represent?

I enclose a picture. Take a look below.

Bryan Parkoff

The two different transistors in the NMOS 6502 are enhancement and depletion mode transistors. The depletion mode transistor is indicated with a fatter body, and it performs the function of a pull-up resistor.

Indeed - it may be worth noting that the public transistor counts usually omit the depletion mode pullups.

Can you confirm that accumulator register is really four NANDs transistors as S/R latch? If it is D flip-flop, it is supposed to be more than four transistors. I have no idea how visual 6502 shows only four transistors as I mentioned earlier. I will look at depletion mode transistors shortly.

Bryan Parkoff

The A reg is indeed a pair of inverters with the feedback broken by a pass gate on phi2 (in visual6502, that's cclk, in Balazs' schematic it's Cp2) and with a pass gate on the input connecting to the Special Bus, controlled by SBAC (aka dpc23_SBAC, aka x4)

If you use the Find button in visual6502 expert mode, you can search for say 'a5' and then zoom in, to see bit 5 of A.

The output of the A reg conditionally drives (is tri-state connected to) the SB and the iDB (aka internal data bus) using a couple more pass gates.

The five main transistors (4 in the pair of inverters and one pass gate) comprise 3 ordinary enhancement mode transistors and 2 depletion mode transistors for the pullups. The 3 enhancement mode transistors have numbers in visual6502: use Find on t1534, t3123 and t1331:
http://www.visual6502.org/JSSim/expert. ... 3123,t1331

I don't think you'd call this an SR latch because it doesn't have set or reset inputs. It's more like a D: it's transparent when the clock is low and the input control (SBAC) is high.

Hope this helps
Ed

Hi Ed,

[Your Message]
The output of the A reg conditionally drives (is tri-state connected to) the SB and the iDB (aka internal data bus) using a couple more pass gates.

The five main transistors (4 in the pair of inverters and one pass gate) comprise 3 ordinary enhancement mode transistors and 2 depletion mode transistors for the pullups. The 3 enhancement mode transistors have numbers in visual6502: use Find on t1534, t3123 and t1331:
http://www.visual6502.org/JSSim/expert. ... 3123,t1331

I don't think you'd call this an SR latch because it doesn't have set or reset inputs. It's more like a D: it's transparent when the clock is low and the input control (SBAC) is high.

[My Message]
I already did Visual 6502 the same thing as you have said how to use “Find”. Did you see some labels on bit 0 of A register in my picture? You are right it is not S / R latch. It does not look like D flip-flop. It is to be buffer.

Are a0 transistor (t2654) and a0’ transistor (t3065) connected to two depletion mode transistors?

Look at my picture below. Notice the blue circle around power, extra transistor, and n146. The extra transistor between power and n146 do not have labels. It looks like its base is wired directly to the n146. What is this?

I think I begin to understand, but I am still figuring while I draw my schematic. This bit 0 of A register has six transistors (excluding SBDB transistor). Two transistors are inverter and four transistors are tri-state. I am not sure if tri-state is supposed to have inverter unless extra wire is connected between any node and transistor.

Three transistors look like that one bit is flowing through around the gate path. If cclk transistor (t1507) is turned on, ‘1’ bit on n146 flows through gate path in cclk transistor toward n737 and it is on the way toward a0 transistor (t2654). a0 transistor is turned on before output is ‘0’ bit on n5. ‘0’ bit on n5 flows toward a0’ transistor (t3065). a0’ transistor is turned off before output is ‘1’ on n146. ‘1’ bit on n146 flows back toward cclk transistor. The cclk transistor’s gate path is connected between n737 and n146.

The gate path between n737 and n146 is disconnected during cclk transistor is turned off while one bit on a0 transistor and a0’ transistor remain unchanged.

The ‘1’ bit or ‘0’ bit on n54 is blocked toward sbac transistor (t1841) from sb0. If n534 from sbac is turned on, sbac transistor’s gate path connects between n54 and n737 while cclk’s gate path is disconnected between n737 and n146.

The acsb transistor and acdb transistor are tristate. They are the same as sbac transistor and cclk transistor.

Take a look at my schematic picture below. Please confirm if it is to be correct. If it is correct, it helps me to understand much clearly before I can continue to draw more schematic picture.

Bryan Parkoff

Hi Bryan

Yes, these two transistors are pull-downs of inverters. Note that 737 is a storage node - the storage node of the D latch. It might be best to see this as a D latch with two clock inputs. If either cclk or SBAC are high then the storage node is updated. If it's cclk, then the update is from the present value - it's recirculating.

This is a pullup. They are not numbered, or selectable in visual6502. Take a look at http://en.wikipedia.org/wiki/Depletion-load_NMOS_logic - the transistor T1 is a pullup. (Note that MOS transistors have a 'gate' connection, not a 'base' connection)

Think of an NMOS transistor as a switch. Like a relay, it's bidirectional. Sometimes the circuit constrains the signal direction and sometimes it doesn't. When the transistor is in a pulldown configuration, you can collect the transistors with their pullup and call it a logic gate. Unless any input is connected through a pass gate (which is the other configuration) in which case that forms a storage node.

You must take care in drawing a tristate symbol, to be sure that you have inferred the right direction, or use a bidirectional tristate symbol (a bit like a 74245)

No, a pass gate is not inverting. It's a switch: on or off. That's a tristate.

Yes, I think you're describing the recirculation when cclk is high.

Indeed - at this point it's a storage node which can accept a new value if SBAC is high.

Yes, if cclk is low and SBAC is high, the register is updated.

They are the same, but they have different roles. They cause the A reg - actually the output inverter whose pulldown is t3065 to drive either the SB or the iDB (or possibly both, in theory.)

Sorry, I find it hard to understand. I think it would be better not to have any vss or vcc labels. Where you have both nodenames and numbers I think you should pair them: cclk (943) for example. It's a single label. More importantly, a0 (737) - labelling the inverter is unclear, it's the wire which holds the value. I recommend you straighten out the kinks, and have both cclk's and sbac's pass gate at the left facing right. Then the recirculating value can take a long loop from the output to the input.

Cheers
Ed

Ed,

Hi, when you hold the shift key and click t1507 on Visual 6502, you will get more information about vcc, vss, or other labels. The n943 wire is not vss. It should be labeled cclk. vss is in different transistor which is connected to n943 and the current flows toward t1507. I think I should remove all vcc and vss, but I leave vcc alone in a0 and a0'.

Drawing schematic is a good start! The rest of my schematic seems to be correct. Thanks for your feedback.

Take care,
Bryan Parkoff

Here's a thought. We see that the A register can only be updated when cclk (phi2) is low. It's updated under the control of SBAC. As you see from a trace:
http://www.visual6502.org/JSSim/expert. ... _SBAC,cclk

But SBAC is already gated by phi1 - by transistor t575 as seen here:
http://www.visual6502.org/JSSim/expert. ... &zoom=12.4
(It's actually gated using node 43 which is a rebuffered phi2 - see http://www.visual6502.org/JSSim/expert. ... &zoom=10.4)

So in fact this is a simple D-latch with a gated clock: SBAC and phi1. We can combine the two pass gates and two inverters into a D-latch with a gated clock input.

Cheers
Ed
(Edit: fixed typo in link)

Hi Ed,


You had given good thought. I wanted to add. If anyone is interested to construct microprocessor from scratch, they can go to the website: http://faculty.lasierra.edu/~ehwang/digitaldesign/.

It is very good explanation, but all use CMOS transistors.



Let me clarify what you are describing above. Only one transistor showed in the schematic is called switch or pass gate. It can be one directional tri-state like one lane traffic. This allows value 1 as Vcc or value 0 as Vss to go through one directional tri-state. It is an example of transistor (1507). It does not have any pull-down nor pull-up.

If I want to build bidirectional pass gate, two directional tri-states are needed to become one bidirectional tri-state.

If I want to build an inverter, then two transistors are needed. One transistor (3065) is pull-down. Its collector is connected to Vout, emitter is connected to Vss, and Vin is connected to base. What happen if there is no pull-up? The Vout may receive undefined value (weak value 0) while transistor (3065) is turned off. This is why second transistor is considered to be load resistor. Its collector is connected to Vcc, emitter is connected to Vout, and base can either be connected to between Vcc and collector or emitter and Vout. When transistor (3065) is turned on, Vout receives value 0 while second transistor (pull-up like bucket) "pumps" (like water) the current from the Vss up to Vcc. When transistor (3065) is turned off, the gate between its emitter and Vout is disconnected, Vout receives value 1 while second transistor (pull-up) "drains" the current from Vcc down to Vout.

Please confirm if I understand clearly as I describe to be correct.

I do a lot of research and am learning how microprocessor works. I took electronic engineering course many years ago which is not included with digital circuits, but I changed my major focusing computer programming. I still like electronic engineering very much. I try to refresh my memory!

Take care,
Bryan Parkoff

Hi Bryan


Thanks for the link! I notice there's an appendix on verilog too.


Physically, MOS transistors are symmetrical: the source and drain are exactly the same. So all pass gates are potentially bidirectional. But sometimes you can look at the circuit around them, see that one side is driven and the other side is not driven, and conclude that a particular pass gate only transfers information in one direction. (Note: to pass information in one direction, it's still necessary for current to be able to flow in both directions: the output side, which is capacitative, will need to be charged or discharged.)


Umm, no. See above. All pass gates are potentially bidirectional. A[/quote]
ssume each one is bidirectional until you've proved otherwise.



Yes!

This is the wrong nomenclature: a FET has a source and drain, and a gate. Vin connects to the gate.

In fact, for depletion pullups, the gate is always connected to Vout. This way, when Vout is low, the pullup is less effective, which saves power, and when Vout rises above the threshold, the pullup becomes more effective, which helps speed.

The water analogy is very useful. Note that it's charge which is moved. The movement of charge is called current, and the result of moving charge is a change in voltage. For FETs, the voltage on the gate is what's important. This is different from bipolar transistors, where current into or out of the base is what's important.

I have a feeling your water might be flowing in the wrong direction. When the inverter's input is high, and the pulldown is on, the dominant effect is water draining from Vout down to ground. There's still a trickle from the pullup, which is never completely off.

When the inverter's input is low, the pulldown is off, and the pullup's trickle of water starts to charge up the Vout. As Vout rises, the trickle increases, until Vout is fully charged to the positive rail.

BTW: my story about considering the A reg as a D-type transparent latch with gated clock. The feedback loop is controlled by Phi2, and so I probably should have said that we only get an update when Phi2 is low. So the clock input is (SBAC and not Phi2). If you wanted to model a little more accurately, you'd observe that both SBAC high and Phi2 high is a problem, because both the feedback and the Special Bus value are driving the same input. Perhaps you'd model that as 'zero wins', and so (SBAC and Phi2) is a Reset input to the D-type.

So, we replace two inverters and two pass gates with a D-type and two and-not gates. The advantage is that we no longer have any feedback or contention to model.

Note this: in modern digital chip design, using transparent latches with gated clocks is for serious experts only! It may be efficient, but it's difficult to analyse and difficult to get it correct.

In this particular case, Node 1505 is another transparent latch clocked by phi2. So the signal is constant when phi2 is low. So the SBAC control line cannot glitch.

Cheers
Ed

Hi Ed,

You explained very well. Source can have two labels as Vcc and Vss. Sometimes, labels can be confusing. We can call power and ground for source. What do you think? The pull-up transistor's collector is connected to source (power). The pull-down transistor's emitter is connected to source (ground). Then, pull-up transistor's emitter and pull-down transistor's collector are connected to drain where they go to Vout. The description should look very clear. Do you agree?

I asked you to look for the blue circle in my picture. You answered pull-up transistor. It is connected to node 146 and t3065. I did not see where second pull-up transistor is connected to t2654. I only see two powers and one ground connected to t2654 and t3065.

I am doing progress while am drawing the schematic. It looks better than before as you suggested earlier.

Take care,
Bryan Parkoff

As Ed said above,
FETs don't have an emitter, colector, or base.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Hi Bryan
In your "blue circle" diagram, the second pullup is just off the bottom edge of the picture. It's immediately to the South or South East of your text "n5"

Personally, I very rarely use the terms "source and drain" for individual terminals - because the transistor is physically symmetric and because I can't remember which is which anyway. For transistors used as switches, it's not important: we're not looking for subtle effects, we just want to know if it's on or off. Likewise I'm not comfortable with the terms Vcc and Vss - power and ground are much more immediately meaningful to me. (This is because of my background and education. I'm sure they are very meaningful to others.)

Cheers
Ed

Hi Ed,

I plan to post images here next couple days, but I don't know how. I rather not to use attachment. I can use "[img][...img]". I know how to use [url][/url] to display images, but I prefer to show image in this post between top paragraph and bottom paragraph instead of in the end of this text so that we can follow up the discussion.

I am still examining clock cycle. I have no idea where cclk (943) come from. I know clk0, clk1out, and clk2out are present in the 6502 chip pinout. No cclk pin is mentioned in any 6502 documentation. How did Visual 6502 designer label cclk pin? It is supposed to be an inverter of clk1out or is identical to clk2out. clk1out is identical to cp1.

I plan to implement 6502 simulator in C++ source code in the future. I am going to study transistor by transistor while drawing schematic.

Take care,
Bryan Parkoff