Hi Bryan
Bryan Parkoff wrote:
If anyone is interested to construct microprocessor from scratch, they can go to the website:
http://faculty.lasierra.edu/~ehwang/digitaldesign/.
Thanks for the link! I notice there's an appendix on verilog too.
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BigEd wrote:
Think of an NMOS transistor as a switch. Like a relay, it's bidirectional. Sometimes the circuit constrains the signal direction and sometimes it doesn't. When the transistor is in a pulldown configuration, you can collect the transistors with their pullup and call it a logic gate. Unless any input is connected through a pass gate (which is the other configuration) in which case that forms a storage node.
You must take care in drawing a tristate symbol, to be sure that you have inferred the right direction, or use a bidirectional tristate symbol (a bit like a 74245)
Let me clarify what you are describing above. Only one transistor showed in the schematic is called switch or pass gate. It can be one directional tri-state like one lane traffic. This allows value 1 as Vcc or value 0 as Vss to go through one directional tri-state. It is an example of transistor (1507). It does not have any pull-down nor pull-up.
Physically, MOS transistors are symmetrical: the source and drain are exactly the same. So all pass gates are potentially bidirectional. But sometimes you can look at the circuit around them, see that one side is driven and the other side is not driven, and conclude that a particular pass gate only transfers information in one direction. (Note: to pass information in one direction, it's still necessary for current to be able to flow in both directions: the output side, which is capacitative, will need to be charged or discharged.)
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If I want to build bidirectional pass gate, two directional tri-states are needed to become one bidirectional tri-state.
Umm, no. See above. All pass gates are potentially bidirectional. A[/quote]
ssume each one is bidirectional until you've proved otherwise.
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If I want to build an inverter, then two transistors are needed. One transistor (3065) is pull-down.
Yes!
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Its collector is connected to Vout, emitter is connected to Vss, and Vin is connected to base.
This is the wrong nomenclature: a FET has a source and drain, and a gate. Vin connects to the gate.
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What happen if there is no pull-up? The Vout may receive undefined value (weak value 0) while transistor (3065) is turned off. This is why second transistor is considered to be load resistor. Its collector is connected to Vcc, emitter is connected to Vout, and base can either be connected to between Vcc and collector or emitter and Vout.
In fact, for depletion pullups, the gate is always connected to Vout. This way, when Vout is low, the pullup is less effective, which saves power, and when Vout rises above the threshold, the pullup becomes more effective, which helps speed.
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When transistor (3065) is turned on, Vout receives value 0 while second transistor (pull-up like bucket) "pumps" (like water) the current from the Vss up to Vcc.
The water analogy is very useful. Note that it's charge which is moved. The movement of charge is called current, and the result of moving charge is a change in voltage. For FETs, the voltage on the gate is what's important. This is different from bipolar transistors, where current into or out of the base is what's important.
I have a feeling your water might be flowing in the wrong direction. When the inverter's input is high, and the pulldown is on, the dominant effect is water draining from Vout down to ground. There's still a trickle from the pullup, which is never completely off.
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When transistor (3065) is turned off, the gate between its emitter and Vout is disconnected, Vout receives value 1 while second transistor (pull-up) "drains" the current from Vcc down to Vout.
When the inverter's input is low, the pulldown is off, and the pullup's trickle of water starts to charge up the Vout. As Vout rises, the trickle increases, until Vout is fully charged to the positive rail.
BTW: my story about considering the A reg as a D-type transparent latch with gated clock. The feedback loop is controlled by Phi2, and so I probably should have said that we only get an update when Phi2 is low. So the clock input is (SBAC and not Phi2). If you wanted to model a little more accurately, you'd observe that both SBAC high and Phi2 high is a problem, because both the feedback and the Special Bus value are driving the same input. Perhaps you'd model that as 'zero wins', and so (SBAC and Phi2) is a Reset input to the D-type.
So, we replace two inverters and two pass gates with a D-type and two and-not gates. The advantage is that we no longer have any feedback or contention to model.
Note this: in modern digital chip design, using transparent latches with gated clocks is for serious experts only! It may be efficient, but it's difficult to analyse and difficult to get it correct.
In this particular case, Node 1505 is another transparent latch clocked by phi2. So the signal is constant when phi2 is low. So the SBAC control line cannot glitch.
Cheers
Ed