Quoting from the following post:
http://forum.6502.org/viewtopic.php?p=24080#p24080


I was wondering what the general rules for the stray capacitance are. So how long will a previously charged polysilicon, metal or diffusion element hold the charge/value if it is not connected to power or ground during a short period of time(when phi1 or phi2 are down)?

Specifically:

1. Will it hold the charge during the off period of phi1 and phi2?
2. Will the size of the connection have an influence on the above? I remember seeing a fairly long connection that was powered through a transistor controlled by phi1 and it seemed to retain the charge in the simulator even though phi1 was down, but I can't find it anymore.

Most simulation will not model leakage, and it's leakage which results in a stored value decaying. Possibly you could simulate this in SPICE, but the runtime would be horrendous.

Most connections, even active area (diffusion), have relatively small capacitance compared to the capacitance of the polysilicon gate. The gate-source and gate-drain capacitances are next largest.

Cheers
Ed

Thanks for your answer Ed, I would be even more grateful if you addressed points 1 & 2.

Btw, I don't have any clue what capacitance is and how it affects the holding and/or losing of value/charge.

Capacitance is the ability to store charge. In a water model, pipes are resistors (thin ones have more resistance) and balloons are capacitors.

For point 1, any node which is presently driven will always be driven many orders of magnitude harder than any leakage. So it's only undriven nodes which might leak. Some latches will be phi1 and others phi2, so they will leak at different times. If both clocks are low (which they briefly are) then all storage nodes leak - but the time of non-overlap is very short.

For point 2, capacitance scales with area or with edge length, depending. But area is the greater effect. So a larger area of diffusion or gate, whatever shape it is, will have more capacitance.

Because gate capacitance dominates, you can ignore the sizes and shapes of all the other layout for this purpose: you care only how big the gate is.

Hope that helps
Ed

In Ed's analogy of the balloon, think of the leakage as a pin hole. Eventually the water stored in the balloon will all leak out, but not in the short time phase 2 is low. Since the NMOS 6502 stored charges this way though, it did have a minimum specified frequency; ie, you couldn't stop the clock indefinitely like you can the CMOS ones. Leakage is unavoidable because the manufacturing process is not perfect; but that leakage is extremely low.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Does the same apply for phi1?

For all practical purposes can we ignore leakage in the visual6502 and just assume that a previously powered connection will remain powered even if temporarily not connected to source or ground due to a phi1 or phi2 low?

The principle would apply anywhere you put charge on a net that has capacitance (which basically means any of them) and then seal it off. It will hold the charge for an amount of time determined by the capacitance and the leakage rate.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Certainly visual6502 doesn't model leakage. As I mentioned earlier, it's pretty unusual to do so. The timescales of leakage are at least 100x greater than the usual timescales of simulation.

Cheers
Ed