Armed with the
transistor-level simulation, we can begin to answer some questions like this.
For the case of JMP, the first operand passes from the IDL (input data latch) to the ALU. So when the second operand is presented, the ALU output latch (called ADD in
Donald Hanson's block diagram) holds the LSB and the IDL holds the MSB of the new PC.
I think these two latches are all of the non-visible byte-sized state in the datapath. There's other hidden state for the pipeline control, and of course the IR (instruction register) is non-visible and byte-sized, but always in use and, as it happens, not physically in the datapath.
In the case of JSR, I was surprised and delighted to find that the stack pointer is used to hold the first operand for 4 cycles, while the SP is passed to the ALU for decrement and the PC is written to the stack. In the cycle that the new SP value is written back to the register, the LSB can be written to PC.
Here are the simulation results:
Code:
A:0001 D:20 RnW:1 PC:0001 SP:fd Sync:1 IR:ea idl:20 alu:fe TCstate:011111
A:0002 D:72 RnW:1 PC:0002 SP:fd Sync:0 IR:20 idl:72 alu:fc TCstate:110111
A:01fd D:00 RnW:1 PC:0003 SP:72 Sync:0 IR:20 idl:00 alu:fd TCstate:111011
A:01fd D:00 RnW:0 PC:0003 SP:72 Sync:0 IR:20 idl:00 alu:fc TCstate:111101
A:01fc D:03 RnW:0 PC:0003 SP:72 Sync:0 IR:20 idl:03 alu:fb TCstate:111110
A:0003 D:5f RnW:1 PC:0003 SP:72 Sync:0 IR:20 idl:5f alu:fb TCstate:101111
A:5f72 D:00 RnW:1 PC:5f72 SP:fb Sync:1 IR:20 idl:00 alu:5f TCstate:011111