I looked at 6502 diagram like datasheet. It does mention that all internal registers are connected to internal data bus and internal address bus. Do it have temporary internal register other than internal data bus?

For example, external address bus is $1000 and external data bus is $4C. The instruction reads "JMP $5F72" 6502 MPU receives $4C and stored in data latch register. It is sent to instruction register while it is in the process to fetch and decode opcode.

Next cycle, external address is $1001 and external data bus is $72. 6502 MPU receives $72 and stored in data latch register. Which register $72 is stored? I suppose to say "Program Counter Low" register or temporary register. "Program Counter Low" and "Program Counter High" are separate registers from "16 bit Program Counter".

Next cycle, external address is $1002 and external data bus is $5F. 6502 MPU receives $5F and stored in data latch register. $72 is copied from temporary register and $5F is copied from data latch register before both $72 and $5F are sent into Program Counter register.

Next cycle, Program Counter register sends $5F72 to the external address bus and external data bus receives next opcode.

Please correct me if I am wrong. Are "internal address bus" and "internal data bus" two separate temporary registers?

Bryan Parkoff

The block diagram doesn't usually show it, but there are a small number of temporary registers in the microprocessor. I *think* the 6502 can get by with just one temporary, but I am pretty sure the 65816 has at least three.

Armed with the transistor-level simulation, we can begin to answer some questions like this.

For the case of JMP, the first operand passes from the IDL (input data latch) to the ALU. So when the second operand is presented, the ALU output latch (called ADD in Donald Hanson's block diagram) holds the LSB and the IDL holds the MSB of the new PC.

I think these two latches are all of the non-visible byte-sized state in the datapath. There's other hidden state for the pipeline control, and of course the IR (instruction register) is non-visible and byte-sized, but always in use and, as it happens, not physically in the datapath.

In the case of JSR, I was surprised and delighted to find that the stack pointer is used to hold the first operand for 4 cycles, while the SP is passed to the ALU for decrement and the PC is written to the stack. In the cycle that the new SP value is written back to the register, the LSB can be written to PC.

Here are the simulation results:

That is just so wrong on so many levels. I love it!

That also helps explain why the stack pointer is only 8-bits wide on the original 6502, and appears near the ALU.

It tickles me that the 6502 internally has the same difficulty with shortage of register space that we have at the machine code level.

We've just released an updated version of the transistor-level simulator which, amongst other things, allows you to go direct to the tabulated bus activity. It looks a little like this:



(And of course you can tweak these URLs to illustrate or explore other situations.)