By fully multiplexing the data and address pins, you can free up a huge number of pins. If you're going to have a cache, this actually works to your advantage, because you can have AD0-AD15, A16-A19 (just for example), AL# (address load; loads A0-A19 into an external up-counter), and UP# (counts A0-A19 up). This lets you spend 1 cycle to load the address register, and N cycles for transferring a cache line.

Or, you can take the MIPS approach and put out A0-A19, CMD0-CMD3, where CMD tells what kind of bus cycle is currently in effect, allowing you to also free up R/W and a handful of others.

That's certainly interesting...

I should confess I was thinking of on-FPGA cache. I think the 250k gate FPGA has approx 180kbit of block RAM and 36kbit of distributed RAM. That's a tiny amount for a 4Gword memory, but in a 6502-like context it could offer a high hit rate on code, and offer a write buffer for peripheral writes.

(I have read elsewhere that FPGA doesn't lend itself well to implementing cache)

Having said all that, I'm not expecting to hit terribly high performance points - might as well get an ARM of some sort. I'm after the interest factor in homebrew CPU, the familiarity of 6502 at slightly higher clock speeds, and a tasteful solution to accessing large memories.

And in any case, nothing precludes a screaming off-chip memory subsystem!

In fact, I'm slightly torn between a CPU-replacement in 40pins, which needs an SBC design, and getting one of the Digilent Spartan boards, which mostly have 16bit-wide memory onboard, together with VGA, PS/2, USB and serial ports, and some tens of I/O too. (If you were set on a 32bit memory subsystem, that would answer the question)

As am I -- I wouldn't dare attempt single-cycle execution at >25MHz with anything else. The 65816 _technically_ has uses a DDR-style bus (since it requires you to do stuff on both low- and high-levels of phase-2), which means at 14MHz, you're really dealing with a 28MHz signaling rate. And it's nigh impossible to drive a 65816 _without_ programmable logic sitting _right_ next to the CPU at those speeds.



Not really; remember how big the caches were on the earliest of 80486 chips? And, remember how big of an improvement they provided?

Concerning going RISC, yes, of course, I would not want to predicate my entire commercial venture on some bizarre tweak of the 6502. However, with interest in the 6502 remaining relatively steady, it seems only logical, to me, that someone, somewhere, should challenge themselves to see how they could improve it, through any means possible. E.g., use of a direct-page cache to make all direct-page references essentially free, for example, or additional instructions making vectored execution of code faster (important for both object oriented and functional programming styles).

After all, it's the magic of discovery and excitement of success that matters here, not real-world practicality.