BigEd wrote:
I should confess I was thinking of on-FPGA cache.
As am I -- I wouldn't dare attempt single-cycle execution at >25MHz with anything else. The 65816 _technically_ has uses a DDR-style bus (since it requires you to do stuff on both low- and high-levels of phase-2), which means at 14MHz, you're really dealing with a 28MHz signaling rate. And it's nigh impossible to drive a 65816 _without_ programmable logic sitting _right_ next to the CPU at those speeds.
Quote:
That's a tiny amount for a 4Gword memory, but in a 6502-like context it could offer a high hit rate on code, and offer a write buffer for peripheral writes.
Not really; remember how big the caches were on the earliest of 80486 chips? And, remember how big of an improvement they provided?
Concerning going RISC, yes, of course, I would not want to predicate my entire commercial venture on some bizarre tweak of the 6502. However, with interest in the 6502 remaining relatively steady, it seems only logical, to me, that someone, somewhere, should challenge themselves to see how they could improve it, through any means possible. E.g., use of a direct-page cache to make all direct-page references essentially free, for example, or additional instructions making vectored execution of code faster (important for both object oriented and functional programming styles).
After all, it's the magic of discovery and excitement of success that matters here, not real-world practicality.