@Dr Jefyll
Oh, thanks for pointing that out. I removed the inline images, which were already attachments to this post.

The first, larger spreadsheet is a map of addressing modes to mnemonics. I have grouped them together (mostly) according to their available addressing modes. The black text is the ...

Here is a scheme I am working on to extend the instructions of the 65c02 to support an orthogonal set of addressing modes. New addressing modes are introduced to round out the existing ones: " (a,y)", "(zp,y)","(zp),x". Addressing mode "r" or pc-relative has been made available to mnemonics besides ...

Sometimes I look at the 65c02 opcode map and don't always like how the designers allocated unused opcodes from the 6502 map to support the new 65c02 instructions.

If one were to make a 65c02-ish soft core which included the same 65c02-specific instructions assigned different locations in the opcode ...

All,
I will consider omitting BBS, BBR, RMB, SMB, but they appear easy to implement and my plan allows for more opcode space via prefix bytes anyway.

MichaelM,
Thanks for the attachment. Do you have a Verilog core of your own?

Thanks, all, for the discussion and links.

I guess I will just bite the proverbial bullet and implement all of WDC's 65c02 opcodes. That way I don't have to "worry" about it. I was just hoping to free up some single-byte opcode space and...those Branch if Bit Set/Reset instructions just don't have ...

The functionality lost by not implementing those instructions will be made up for in the 32-bit (orthogonal) extension to the instruction set. Plus, it would free those locations in the opcode map.

So, do those 65c02 instructions permeate most of 6502 software? That is what I would like to know ...

Hi, MichaelM.

I want to do the 65c02 opcodes if they are heavily used in the 6502 software "repertoire". So, that's why I was wondering if I REALLY need to do, say, TRB, TSB, WAI, STZ, et al.

I remember seeing that Neill Parker page sometime back. I like the breakdown of the bit patterns. Thanks ...

The 65c02 adds new mnemonics and addressing modes to the instruction set of the original NMOS 6502. The Western Design Center's datasheet for their 65c02 has a nice opcode matrix (on page 22) here: http://www.westerndesigncenter.com/wdc/documentation/w65c02s.pdf .

I am considering a Verilog FPGA ...

kc5tja said... LOL. True. Why he didn't use an SX instead of the Atmel chip is beyond me. An SX48 would have rocked his world. Oh, well.

I've never had any trouble using WDC's 65xx in a solderless breadboard...even at 25 MHz, but typically lower than 14.

Garth, do your comments apply to new chips or do you believe your advice still stands on chips from, say, 5 years ago?

Not trying to argue (too much) just saying.

Thanks.
--Steve

May I ask: How much is the CPLD you are using for this and what package was it?

Thanks.

You are storing the filebuffers in the ATMega's on chip RAM?

The Propeller microcontroller from Parallax can feed it. But, one might as well just use the Propeller as his video solution then, unless one needs a higher color depth.

Could you descibe why the file system would be more limited if it were handled my the ATMega32?

Thanks!

Um...I don't know how many vias I have. batchpcb.com's service has no restriction on number of holes or vias. I think the largest drill size is 0.5 inch or 500 mils (thous). My board is two-layer. (I understand they have a 4-layer option for $8 per square inch + $10 per order setup fee.) I am not ...