Hello @Jefffrey

I think your project has stopped working on the website: https://lambduh.neocities.org/blocks/
In my case, the website does not respond to the step/run/reset buttons.

The situation is similar with ADC # (opcode 69) in state (T0+T2) half 2 - only the data latch is connected to the DB bus and we have active a DL/DB signal - but in this case visual6502 reports the state of the DB bus as 0xff
Does the difference result from the differences in the construction of the ...

Hey, I thought I already understood the rules between data transfer between registers via BUS. But one thing is bothering me. I noticed that in state T1 half 2, for the data transfer instructions between registers (TXA, TYA, TXS, TAY, TAX, TSX). Visual6502 shows that the SB and DB states depend on ...

Hey, I'm wondering how the alucout signal works - I understand that it is set when the result of the ALU operation does not fit into 8 bits in ALU - but do I understand correctly that this only happens in the second half of the cycle? How long is this signal active? IIs it deactivated if there is no ...

Very cool project - I use it to debug my emulator.
However, one thing bothers me - in your project you used a modified block diagram, which causes some differences compared to what viusal6502 shows.

One of the differences I noticed is TXS - the modified diagram forces an update of the S register to ...