If you've enjoyed Ben's videos and are starting a 65C816 project you might want to give my own series about this processor a watch. https://www.youtube.com/watch?v=sdFXc0Rkpvc&list=PLdGm_pyUmoII9D16mzw-XsJjHKi3f1kqT

Notably, I talk about designing the glue logic in more detail than Ben did, I ...

BDD has agreed to my republishing some of his schematics for his POC V1 and below are those (partial) schematics with my additions. My modifications to the original design were to the RAM (71256SA) and the serial I/O (65c51). I don't have a RT clock (yet), but I'll add one when I get the basic ...

also instead of a slow external clock with an NE555 or similar, you can just use the arduino as the clock source so it's always fully in sync
A great idea! However, my knowledge of the arduino is even more limited than my knowledge of the 6502 family. I'll see if I can figure out how to do this ...

Background:

I have a similar version to Ben's but I dropped the binary (the hex was more useful for me) and added some code to try and decode some of the op codes so I didn't have to keep referring back to the data sheet to look them up.

Here's the code, forewarning I never cleaned this up ...

Thanks to everyone who's helped with this problem so far! The board is now correctly running the test program on the slow clock with all chips in place and has been running for about an hour. I'll try the more complex firmware tomorrow.

I'm thinking that the extremely noisy signals in my third ...

Good find! ABT was floating and it's now tied high. Thanks!

A clear, monochrome schematic would be *VERY* helpful. Scope traces alone aren’t all that useful without knowing how the circuit was designed.

As the others noted, you may have an address bus wiring error. However, the mess seen on D0 and D1 suggests there may other issues, possibly timing-related ...

I'm also thinking a swapped address line, but on the MEGA.

The reset vector should be FFFC but traced as FFFA. ... 1100(C) vs ... 1010(A) similarly for FFFD but it's traced as FFFB. 1101(D) vs 1011(B). The ROM contains FFFA:EA and FFFB:EA and if that is the address it receives that is what it ...

Good point about trying to read from $D000 and actually reading from $B000. I didn’t notice that until you pointed it out. I believe that the cpu is actually reading from $D000, because I can see the chip select for the ACIA go low when I single step through that read operation. I’ve checked both ...

Background:
I'm creating an 65c816 SBC based on the POC-V1 design of BigDumbDinosaur. My board differs from BDD's in that I'm using a 15ns 28c256 EEPROM (rather than BDD's 27c256) and two 15ns 71256SA SRAMs (rather than BDD's single SMT SRAM). Also, at the moment, I'm using a 6551 for serial I/O ...

Hello, everyone! I'm ssturgis and I first got introduced to the 6502 world when I bought a KIM-1 back in 1976. In the following years, I built-up a fairly complete KIM-1 based system using components from RNB Enterprises, Hudson Digital, Micro Technology Limited, and Problem Solver Systems. At the ...