Search found 8 matches

by Berzerkula
Tue Nov 25, 2025 5:01 am
Forum: Programmable Logic
Topic: CPLD and Verilog Learning Experiment with 8 5x7 Displays
Replies: 1
Views: 815

CPLD and Verilog Learning Experiment with 8 5x7 Displays

Greetings,

I first got started with CPLD's with the CPLD trainer from plasmo. I only dabbled a bit from examples in books and others. This time I took on another challenge. I have a bunch of TIL305/LTP305/LRT1704 5x7 dot matrix displays. Also, some newer ones from Pimoroni. My goal? Output the hex ...
by Berzerkula
Wed Sep 07, 2022 8:32 am
Forum: Programmable Logic
Topic: CPLD + 6502 Trainer
Replies: 80
Views: 90993

Re: CPLD + 6502 Trainer

Looking at the datasheets, pin assignments of DIP AS6C1008 are the same as pin assignments of SOJ CY7C109. Pin 1 is NC, pins 13-15, pins 17-21 are data, chip enable active low is 22, chip enable active high is 30, output enable is 24 and write enable is 29. VCC is 32 and GND is 16. I don't see any ...
by Berzerkula
Tue Sep 06, 2022 9:28 pm
Forum: Programmable Logic
Topic: CPLD + 6502 Trainer
Replies: 80
Views: 90993

Re: CPLD + 6502 Trainer

The short answer is: yes, it is pin-to-pin connections between AS6C1008 and CY7C109. CS2 (pin 30) of CY7C109 and AS6C1008 is enabled by driving high with CPLD output.
Bill

Hello Bill,

I was wondering if it was a pin to pin connection because the surface mount part pinouts differ from the DIP ...
by Berzerkula
Wed Aug 24, 2022 4:49 am
Forum: Programmable Logic
Topic: CPLD + 6502 Trainer
Replies: 80
Views: 90993

Re: CPLD + 6502 Trainer

I never documented the design! Hmmm, I've made several designs in that topic area (piggyback VGA); you can see an assembled stack here .

I'll fix that soon, but attached are schematic and gerber photoplots. The short answer is: yes, it is pin-to-pin connections between AS6C1008 and CY7C109. CS2 ...
by Berzerkula
Wed Aug 24, 2022 1:21 am
Forum: Programmable Logic
Topic: CPLD + 6502 Trainer
Replies: 80
Views: 90993

Re: CPLD + 6502 Trainer

The modified trainer appears to work at 25.175MHz. Adjusting the baud clock generator and testing with 29.5MHz clock, I see it'll boot and execute the monitor commands but memory diagnostic is failing intermittently so I believe the design is on the hairy edge at 29.5MHz. I'm a bit disappointed ...
by Berzerkula
Sun Jul 31, 2022 2:42 am
Forum: Programmable Logic
Topic: CPLD + 6502 Trainer
Replies: 80
Views: 90993

Re: CPLD + 6502 Trainer

Very nice ROM emulator! I like the idea of emulators or added functions in form of 32-pin DIP or 40-pin DIP.

In this particular case the CPLD is flexible and has spare capacity so diagnostic function and/or test points can be easily added to solve a specific problem during hardware development ...
by Berzerkula
Sat Jul 09, 2022 6:18 pm
Forum: Programmable Logic
Topic: CPLD + 6502 Trainer
Replies: 80
Views: 90993

Re: CPLD + 6502 Trainer

I have not tried 6809, yet. It needs nearly 40 manual wiring; I have a bit of time this weekend so I may give it a try.

Are you using Altera(Intel) CPLD or Atmel? If you are new to CPLD, getting CPLD tool chain to work is probably the most challenging part of the project.
Bill

I have on hand ...
by Berzerkula
Fri Jul 08, 2022 2:49 pm
Forum: Programmable Logic
Topic: CPLD + 6502 Trainer
Replies: 80
Views: 90993

Re: CPLD + 6502 Trainer

Very promising for retro investigators especially if 6809 proves out. One board for comparing the major players in the vintage age.

I am starting to assemble the PCB and have Z80, 6502 and 6809. Interested in 6809, as well. 6809E with external Q/E via a quadrature clock may be interesting with ...