Here's an omnibus version that can do vector pull rewrite for either a W65C02, or a W65C816 in either native or W65C02 emulation modes.

I added a buffer with three state outputs, to keep the offset at $0 when there's no active input coming from any of the 7 hardware IRQ lines.

Thanks for the feedback, everyone.

Sorry for posting it in color, I'll be more respectful and post only black and white from now on.

Here's the same circuit with suggested changes HC family logic, and a 0.45 Vf Schottky diode and 3.3K resistor for the IRQ pull.

I've added notations showing that ...

Here's a circuit that adds six more IRQ vectors to the W65C816, for a total of seven, triggered by hardware priority.

The circuit detects when the IRQ vector $FFEE-FFEF is being pulled using a 3-to-8 encoder to detect when E and VPB are low, indicating that an interrupt vector is being fetched in ...

One good thing about [the 16550C] is it has auto hardware flow control and FIFOs, making more efficient use of the CPU time.
That is also true of the NXP/TI/Exar 26/88-series of UARTs. Plus these UARTs have dual channels and a precision timer, the latter which is something that is not in the 1655x ...

Also if you're feeling industrious in the future you could swap out the top jumpers for a '573 latch and make the bit count programmable by the 6502. If you're even more industrious you could swap out the bottom jumpers for another latch and the NAND gate U6A for a '521 comparator; feeding both ...

Interesting approach! Agreed that it is a lot of chips and it might be more practical to replace the 65C51 with something else (have you looked at the 16C550C in DIP?), but we're here to have fun not be practical! :-)

If you enable receiver interrupts, you should also get interrupts for ...

Hey Alan, that's me who was chatting to you on YouTube. Good catch on needing to divide the 1.8432Mhz signal down.

Just to make sure I'm understanding. You're using the bottom set of jumpers to select the baud rate and the top set of jumpers to select the total number of bits?
Yep, that's the ...

Here's what I would like to try. It's the same approach as using the PB6 counter on a VIA, but without the VIA: I use a 74HC590 binary counter cascading into a 74HC191 binary counter, with a 74HC74 flip-flop driving DSRB high ("not ready") whenever the CPU writes to the data transmit register ...

I'd like to note that, in order to easily protect the I/O area used by the MMU, it would
be trivial to arrange an ABORTB if the PID of the currently executing process is nonzero when access
is attempted to the controller side of the MMU.

I'm starting with Adrien Kohlbecker's 65816 breakout board.

I am aiming at parallel processing, using DMA channels based on address decoding, so that each CPU sees its even numbered banks as the opposite CPU's odd numbered banks.

I have also implemented a programmable interrupt controller that ...

Hi, I'm finally joining the forums, after lurking for a while. To start off with, thank you SO MUCH for the expertise made available here.

I unwrapped my first Commodore 64 on Christmas Day, 1984, in Louisville, Kentucky, where I still live. The Programmer's Reference Manual was a revelation to me ...