https://youtu.be/nkJh0ZdM1hA

What did they talk about in the other 70 episodes?

I put mine on a VIA

I'll make a few other observations...

1- What clock rate are you running the CPU at? I don't recall seeing it mentioned. Also, which CPU is it?

2- CA2... your ISR toggles it, but it's purpose is not described. Is it handshake to the external device?

3- Your ISR increments an index which is 8 ...

CA2 is tied to the bus enable of my downstream device. Without that, there’s no data to read. Hmm... Dunno if this is feasible with your setup, but maybe you can solve the problem by arranging things so both edges of the CA2 pulse have significance. Let the ISR begin by setting CA2 low, which ...

irq:
pha
phx
lda #(via_pcr_ca2_lo)
sta via_pcr

; load the char and clear the interrupt

lda via_a_data

; store the char in the ftdi buffer at the write pointer

ldx ftdi_write_pointer
sta ftdi_buffer,x
lda #(via_pcr_ca2_hi)
sta via_pcr

inc ftdi_write_pointer
plx
pla
rti

Which ...

irq:
pha
phx
lda #(via_pcr_ca2_lo)
sta via_pcr

; load the char and clear the interrupt

lda via_a_data

; store the char in the ftdi buffer at the write pointer

ldx ftdi_write_pointer
sta ftdi_buffer,x
lda #(via_pcr_ca2_hi)
sta via_pcr

inc ftdi_write_pointer
plx
pla
rti

Thanks. That’s plausible. I AM writing to the PCR in my ISR to set CA2 low before I read port A ‘cos CA2 is tied to the bus enable of my downstream device. Without that, there’s no data to read.

I did investigate the “pulse is too narrow” hypothesis by putting a monostable in between my downstream ...

I'm guessing that the spike on CA1 (at the same time as the rising edge of CA2) is the result of the device providing more data immediately after the CA2 handshake: device says "I have data" on CA1, you get an interrupt, CA2 says "OK, read it", CA1 goes high and then low again because there's ...

I have set up a 65C22N to generate an IRQ on the falling edge of CA1 to read data from a downstream device.
My downstream device generates a falling edge on CA1 when there's data ready for the VIA to read from the downstream device.
When I stream data to the VIA at low speed this works reliably ...