Finally I've found the reason for the strange behavior: propagation delay.
My TI 74HCT00N needs 5 ns for a gate pass, so the A12...A14 ist 20 ns befor A0, A1 and A2.
That is too much for the way I drive the 374er.
And I've found a solution.

Many thinking, measuring, testing.. I've documented it on ...

I've measured the time, the NAND gates needs to operate:

Thats means the time between

A12 is going low (blue curve)
A12...A14 (NAND cascade) is going low (yellow curve)

and it is 15.4 ns.

In the going-high-phase the NAND-Cascade needs 16.8 ns.

Have to think about the timing will differ on ...

Hello Friends,

thanks for your help so far.

I think the reason will bei the missing involving of the CPU clock and I will alter and check my circuit in this aspect.

Momentarily I read the docs from http://wilsonminesco.com/6502primer/addr_decoding.html . They are very helpful. Will read a little ...

Okay, I've zoomed really deep in with my scope and found a 20 ns signal fall at the middle 374.
But only an the middle one, not on the left and not on the right one.

It's only 20 ns on low but this seems to be enough to trigger the 374er to update.

Yellow line on the scope is the NOT(A12 AND A13 ...

I'm going nuts...

I used a 74HC374 D-Latch in my 6502 Breadboard Computer to set an 8-LED-Output sucessfully (at address 0x7000)

With the same principle I want to do a 3-digit-7-segment-display and give them the addresses 0x7001 (left), 0x7002 (middle) and 0x7004 (right).

When writing to 0x7000 ...