What I've "settled on" over the last week is something like the following:

Half (*1) a 139 to manage Phi2 and R/W into /OE and /WE.
A15 to /CS of a 32kx8 SRAM (I have a CMOS one someone gave me years ago - that'll work with an old NMOS 6502? ).
A15 to G1 of a 138, with A14-A12 decoding the top 32k ...

Thank you both.

I've been reading a lot (including this forum, and also the primer) before joining, so both of you have already contributed to my thinking.

The HCT comment even predicted one of my next questions.

Now I need to re-check what's available from local (New Zealand) suppliers. Will ...

I'm looking at options for address decoding and came up with a question, would appreciate any comment.

Say I used an n to m decoder (e.g. 74LS156), with open collector outputs, but I wanted the decoding to be asymmetric (e.g. to get blocks of 8k, 8k, and 16k, out of 32k), would it be practical to ...