Hi all;
I was reading through the instruction timing chart (table 6-5) of WDC's W65C02S datasheet (February 2004), as one does, and got a little confused when it comes to the behaviour of the BBRx and BBSx instructions.
It is my understanding that they have only 1 addressing mode which is really a ...
Search found 3 matches
- Fri Jul 22, 2022 11:16 am
- Forum: Programming
- Topic: Instruction timing of BBRx and BBSx
- Replies: 3
- Views: 980
- Fri Dec 24, 2021 10:56 am
- Forum: Hardware
- Topic: Interfacing R65C02 to HC logic
- Replies: 5
- Views: 744
Re: Interfacing R65C02 to HC logic
Thank you all for your feedback. I'm taking several points from this:
When an IC is declared "TTL compatible" it's more of a "for some values of TTL" statement than a formal declaration of adherence to the exact TTL thresholds.
You need some kind of historical awareness of what characteristics ...
When an IC is declared "TTL compatible" it's more of a "for some values of TTL" statement than a formal declaration of adherence to the exact TTL thresholds.
You need some kind of historical awareness of what characteristics ...
- Sun Dec 19, 2021 11:57 am
- Forum: Hardware
- Topic: Interfacing R65C02 to HC logic
- Replies: 5
- Views: 744
Interfacing R65C02 to HC logic
Hi all;
I am measuring a solid 5V logic H level from the address bus output of a R65C02 that I am doing a project with, but the chip is designed to work at TTL levels and the Rockwell datasheet promises only at least 2.4V for a logic H.
In general I am interfacing to it using HCT logic, but as I ...
I am measuring a solid 5V logic H level from the address bus output of a R65C02 that I am doing a project with, but the chip is designed to work at TTL levels and the Rockwell datasheet promises only at least 2.4V for a logic H.
In general I am interfacing to it using HCT logic, but as I ...