Search found 153 matches

by dmsc
Tue Mar 17, 2026 2:57 pm
Forum: Programmable Logic
Topic: Arlet core register timing
Replies: 3
Views: 1807

Re: Arlet core register timing

Hi!

I suspect you are not reading the verilog code correctly.

"load_reg" uses a non-blocking assignment (<=) inside an always @(posedge clk) block; making it a registered signal, stable throughout the clock cycle.
"write_register" uses a blocking assignment (=) inside an always @* block; making it ...
by dmsc
Thu Mar 05, 2026 10:34 pm
Forum: Programming
Topic: Announcing VC83 BASIC, a BASIC interpreter for the 6502
Replies: 21
Views: 1617

Re: Announcing VC83 BASIC, a BASIC interpreter for the 6502

Hi!

This is great, another open source BASIC interpreter for the 6502 :-)

I made a minimal port to the Atari 8-bit, only including a "DOS" statement. IMHO, for this to be more useful, you should add (minimal) "SAVE" and "LOAD" statements.

I suppose the floating-point support is written by ...
by dmsc
Fri Jan 02, 2026 2:40 am
Forum: Programming
Topic: Bug in 6502 BRK.
Replies: 18
Views: 1464

Re: Bug in 6502 BRK.

Hi!

Adding to the above, for more details you can see page 45 of the Altirra Hardware manual, at https://www.virtualdub.org/downloads/Altirra%20Hardware%20Reference%20Manual.pdf, on "overlapping interrupts", that states:

Overlapping interrupts

...There are no issues with an overlapping IRQ ...
by dmsc
Fri Jan 02, 2026 12:45 am
Forum: Programming
Topic: Bug in 6502 BRK.
Replies: 18
Views: 1464

Re: Bug in 6502 BRK.

Adding to the above, for more details you can see page 45 of the Altirra Hardware manual, at https://www.virtualdub.org/downloads/Altirra%20Hardware%20Reference%20Manual.pdf, on "overlapping interrupts", that states:


Overlapping interrupts

It is possible for the 6502 to first begin executing ...
by dmsc
Fri Jan 02, 2026 12:38 am
Forum: Programming
Topic: Bug in 6502 BRK.
Replies: 18
Views: 1464

Re: Bug in 6502 BRK.

Hi!

It is in fact a lot easier to deal with BRK, you just have to see if the flags pushed to the stack has the B bit set.

There is a misunderstanding here about the BRK: the problem is not that the BRK is missed by an IRQ, it is that an NMI can mask a BRK instruction - the CPU jumps to the NMI ...
by dmsc
Sat Oct 11, 2025 2:57 pm
Forum: Programming
Topic: 16-bit/32-bit 65C816 random number generator
Replies: 37
Views: 3058

Re: 16-bit/32-bit 65C816 random number generator

Hi!

It is great that you are testing this properly!

After the discussion about a 24-bit PRNG in this thread I got motivated to do a better job of making a 16-bit random number generator than some other recent efforts which I won't share!

I had been looking back on this other thread where a ...
by dmsc
Sat Oct 11, 2025 2:31 pm
Forum: Programming
Topic: fast 24 bit PRNG
Replies: 14
Views: 2149

Re: fast 24 bit PRNG

Hi!

Just found this fast 24 bit PRNG algorithm by Wim Couwenberg:

lda a ; Operation 7 (with carry clear).
asl
eor b
sta b
rol ; Operation 9.
eor c
sta c
eor a ; Operation 5.
sta a
lda b ; Operation 15.
ror
eor c
sta c
eor b ; Operation 6.
sta b

For more details: https://wimcouwenberg.wordpress ...
by dmsc
Mon Jun 23, 2025 2:30 am
Forum: EhBASIC
Topic: A curious bug in EhBasic
Replies: 9
Views: 2933

Re: A curious bug in EhBasic

Hi!

That seems to be a nice patch, but it assumes that the Y register can be stomped, which might need further investigation. SKO hinted at this in the initial post.
Yes, this is true.

I scanned the usage of the above code a little, and it is only used on "CLEAR", "NEW" and "RUN", and in each ...
by dmsc
Sun Jun 22, 2025 9:32 pm
Forum: EhBASIC
Topic: A curious bug in EhBasic
Replies: 9
Views: 2933

Re: A curious bug in EhBasic

Hi!

Hi everyone,

The issue is with the following code:


; flush stack and clear continue flag

LAB_1491
LDX #des_sk ; set descriptor stack pointer
STX next_s ; save descriptor stack pointer
PLA ; pull return address low byte
TAX ; copy return address low byte
PLA ; pull return address high ...
by dmsc
Tue Jun 17, 2025 1:45 am
Forum: Programming
Topic: Comparing 6502 multiply routines
Replies: 51
Views: 26462

Re: Comparing 6502 multiply routines

Hi!

Over the weekend, I found myself writing a routine to calculate "factor1*factor2+offset", a multiply-add, with X and Y 8 bit numbers, and P an 16 bit number. Some of the routines can be reworked to do this faster, I settled in the mult21 with adding only one "adc" at the end, for 20 bytes ...
by dmsc
Fri Jan 17, 2025 2:22 am
Forum: Programming
Topic: tiny serial bootloader with support for remote debugging
Replies: 23
Views: 5676

Re: tiny serial bootloader with support for remote debugging

Hi!

My small serial bootloader is now published on Github ( https://github.com/tius/tinyload65 ).


Great to see the optimized software serial code :)

In the "optimized tx_byte for bit 0" you can chop two bytes by using ASL instead of ADC:
sta _tmp ; 3
lda #_OUT_LO ; 2
sta SERIAL_TX_PORT ; 4 ...
by dmsc
Wed Jan 08, 2025 12:49 am
Forum: Hardware
Topic: How are GND & data lines pared in parallel I/O cable❓
Replies: 25
Views: 6300

Re: How are GND & data lines pared in parallel I/O cable❓

Hi!

Does the port on the back of your device look like this, and it is labeled RS-232C?

If so, that's a serial port (sometimes called a COM port) and not a parallel port. The cabling is different for those ports and there indeed is a "crossover" cable available for that kind of port. That was my ...
by dmsc
Wed Jan 08, 2025 12:33 am
Forum: Programming
Topic: A 6502 divide routine
Replies: 18
Views: 4877

Re: A 6502 divide routine

The worst cases in the divide routine that I have presented occur, ironically enough, when the divisor is a power of two. And the worst of the worst occurs when the divisor is 1 and the dividend is 32767. This case requires almost 2000 cycles to produce the result. For this reason, it seems ...
by dmsc
Mon Jan 06, 2025 2:10 pm
Forum: Hardware
Topic: How are GND & data lines pared in parallel I/O cable❓
Replies: 25
Views: 6300

Re: How are GND & data lines pared in parallel I/O cable❓

Hello 0010 all,

Mea culpa, mea maxima etcetera, mentioning "printer" was my mistake (no Centronics connector to be seem within miles) !


The IEEE-1284 standard is not a "printer" standard, is a bi-directional parallel communication protocol between PC computers and other devices.

Did you read ...
by dmsc
Mon Jan 06, 2025 2:55 am
Forum: Hardware
Topic: How are GND & data lines pared in parallel I/O cable❓
Replies: 25
Views: 6300

Re: How are GND & data lines pared in parallel I/O cable❓

Hi!

There is not enough grounds in the DB25 interface to cover all signals, so the IEEE 1284 standard simply reuses grounds, and the standard explicitly says that you need a 36pin connector at the peripheral side to get the full speed (of more than 2MB/s).

See https://www.ti.com/lit/an/scea013 ...