I seem to be encountering conflicting information about how the zero flag (and other flags in the processor status register) are set. On the one hand, I've read that the zero flag is set when the accumulator becomes 0. On the other, I've read that it's when any arithmetic/logic instruction generates ...

Very interesting. Thanks!

Referring to this manual , I'm currently studying the timing of absolute, X addressing for read-modify-write instructions (section A. 4.4.). In cycles 3 and 4, the address bus has the exact same values, but data is only fetched in cycle 4. The address bus is marked with "(discarded)" in T3. Why is ...

Thanks very much, both of you!

I'm currently writing a VHDL 6502 core for an FPGA. I'm trying to stay as true to the original microarchitecture as possible in my design, and have been using this block diagram to do so. I'm currently working on the control logic for implementing absolute addressing. I have PCL, PCH, ABL, and ABH ...

In an effort to stay as true to the original bus timing as possible, I think I've come up with a better design yet. I realize this is probably overkill at this point, since, as Garth pointed out, some of the design constraints I was concerned with are loosened (or null) because I'm doing this ...

I will be using exclusively block RAM for memory, internal to the FPGA, so I think this timing scheme should at least work for that application. I plan to build the whole system in the fabric of the FPGA (i.e. no external ICs). Given that, I think what I've got in the latest diagram should work, but ...

I've attached a new timing diagram to this post. Now, CLK is labeled Φ2, and I'm changing the address on falling edges. As suggested, I'm showing how I might use a synchronous FPGA block RAM as a pseudo-asynchronous RAM by clocking data out of the synchronous RAM on falling edges and capturing that ...

Thanks for the replies, everyone.

Welcome! You've got a good example there of the 6502's design style - it does indeed get more performance than you'd expect, in that data arriving on the data bus towards the end of one cycle can be output on the address bus early in the next cycle. You can do ...

Thanks!

In regard to your last point, if CLK were Φ1, it would then be correct to show the address changing on rising edges of CLK, right? Since the two clocks are essentially complements of each other (with some additional wiggle room, I've gathered from reading, to ensure no overlapping). I'm ...

Greetings,

I'm currently working on implementing my own 6502 in a Xilinx Spartan 6 LX9 FPGA. I've been studying the hardware manual and various other resources online, but one thing I'm struggling with is the timing for instructions. For instance, I'm looking at the timing for absolute addressing ...