Hi folks, I used CA65 myself a while ago. I'm programming for a VIC 20. I have to figure it out again, it's been so long. I will figure it out again. I can assemble but I can link going by my notes. It's a good assembler.

This is a basic hookup of the internal 8K ram to the character rom. VICBNK0 would drive the first 8K SRAM. Add another 8K to this board and you can use the RAM under the character ROM.

VIC_Down_Under.pdf

This will add a 4-bit register @ $9200, by breaking up the IO @ $9000 with new locations @ $9000 (don't use), $9100 for selecting existing VIAs, $9200 (new write only register), leaving an extra IO starting @ $9300. I tried to make the labels intuitive. The circuit for the ...

If you are interested in putting RAM under your ROM, like on the C64, you're in luck. I've built such a circuit using discrete logic, although it fits nicely on a Xilinx XC9536, not an XL. It goes nicely with my 8K internal RAM board. Just let me know if you're interested, I can post drawings if you ...

I was thinking more like !(VDA || VPA) == 0, so when there is a valid address as shown in the timing diagram, the bank address is available. This been tried? Oh, wait, I see a 3 ns gap between the VDA/VPA becoming valid and the bank address being available.

Thanks Dr. Jefyll.

My thought was to just use *(VDA # VPA). This does tell us that the whole address is available, including the bank bits. The timing diagram below the PHI2 diagram shows that VDA and VPA change at the right time, the same way you validate addressing memory. The bank is held until ...

I was just looking at the timing diagrams in the Western Design 65C816 and I noticed the answer to bank address latching made easy.

My first clue is these two signals that are supplied by the CPU are already used in every design I've seen. All you need to do is look at lines 2,3 and 4 of the ...

Will there be a tutorial on how to set up my Macbook Pro with Apple hardware. It looks like PALAsm is being used to program a number of devices. I'm new with my Macbook Pro and need help in this area.

...And thanks so much for putting out this Youtube series.

The Series sure helped.

I am curious about the 65C816 data sheet, AC characteristics has a list of the max. clock speeds for different voltages. If I plan on running about 3.5 mhz, can I use the 4 mhz timings for that speed, even if I am using 5 volts?

I purchased a program platform from Atmel and would like to find out if there are any open source programs to upload to the programmer. I have WinCUPL and wanted to see how the ATF1504AS works, but I can't upload my PLD file to the programmer. Am I at the mercy of Atmel or is there an alternative? I ...

Does anyone have a Super CPU and know what is in bank 1, where the STA is referencing in the above code snippet? Can these values be stored elsewhere, or even at all, since I'm not using a SuperCPU? It looks like it could be a new brk vector. Is there code in bank 1 of the SuperCPU, or is it ...

Thanks for the explanation.

Can you tell us more about this 65816 in a vic-20?

What I am attempting is to give the VIC 20 the power of the 65C816. I started by adding logic to put RAM under the kernal and basic roms, plus two 4K blocks of RAM under the character rom. This is all controlled by a register that I mapped to ...

I'm not real knowledgeable about the 65c816, but I am trying to learn. I remember in the past looking at the schematic of the dynamic ram refresh circuit of the Apple IIE and it required a clock that twice the system clock. Is it possible that the MX signal could be used for refreshing D-ram? Or is ...