What you are doing is pretty cool! You mentioned sprites earlier, I would think you would need at least 1 sprite for a hardware mouse pointer. Maybe instead of accessing memory for it have some registers for it's bitmap or a small rom to be able to select different kinds, pointer, hourglass etc ...

Here is the Verilog source for my latest X6510 cpu's. Big thanks to Ed for getting me a version of Klaus' test suite. It found 2 more bugs so do not use anything I may have posted before. I also added the RDY input signal to be more flexible. I am posting a 32 and 16 bit data bus version of the ...

It's great to see people fluent in Verilog post on this site.
Thanks, but I would not say that, I can usually hack at it until it works, I have no formal training any any of the languages I actually use except for C++. Trying to write code for 10+ years helps me out. In college I took Fortran and ...

Sounds good!

I have been around for a few months but never really introduced myself...

I'm Ken and work for Xerox in Wilsonville Oregon. I am a programmer in the print head group.

I had a C64 in high school, that got me started. Got a AS degree in electronics from BMCC where one of my projects was working with ...

I have a new processor design that removes the memory pipeline delay (that was required for using bram normally) from my original design. Unfortunately I have not been able to test it with normal sram. How I tested it was by clocking the bram on the negative edge of the clock to simulate normal sram ...

if (lineCS && cpuAB == 5'b10000) //horizontal offset
hoffset <= cpuDO;
if (lineCS && cpuAB == 5'b10001) //vertical offset
voffset <= cpuDO;

Are you not missing these in your new case statement?

I would suggest you add a default to your case statement just in case you get a situation you are ...

On the MINEO are the address and data lines separate fpga inputs/outputs for each ram chip?

I am not positive but it looks like you are wanting to keep an 8 bit data bus?

If that is true it will be hard to execute multiple instructions because of the available memory bandwidth for loading instructions ahead of time along with doing the operand accesses, that is why my fastest design is a ...

SID is not working yet and IEC interface very unstable...

I included some other files to show how the memory interfacing and debug stuff was done...

Feedback on my code is appreciated, I do not program in this language for a living...

I would also be interested in knowing if anyone is able to implement this in their own system.
Remember to register the ...

I have a von Neumann version of my cpu working (no dual ported memory required). I have only run it on my Spartan 6 with only 1 port of the Bram hooked up. I have been unable to test it with the external rams because I cannot get the video to work correctly on the Spartan 3 development board I have ...

things that have to do with the individual bytes

For a 6502 that is pretty much all things. If you want to do 32 bit arithmetic inside the cpu instead of 8 you could do that but there would not be much existing code that would work also. Immediate instructions would have to be 5 bytes instead of ...

There really is no other cache unless you want to count the 12 byte instruction register. This is more like a shift register that shifts to the next instruction while shifting in new instruction fetches as there becomes room. When ever there is a branch or jmp or interrupt it gets cleared and starts ...

I think you had it right, I just was not as clear in my description as I could have been...

In the current implementation both external ram/rom and internal cache (512 bytes) are both dual ported.
The external is dual ported so that I can simultaneously read an instruction and read or write an ...