If all modern CPUs use master-slave flip flops, does that mean the PC has to be copied to the address bus register a cycle ahead of time?

Single meaning, that the output changes as soon as it gets written to, vs double, as in a "slave-master" flip-flop where the second latch waits for the first latch to finish latching before it updates the output.

The fact that most websites describe the fetch cycle in the fetch-decode-execute ...

I don't know if all these opcodes can fit in 256, nor would I have any idea of what price the 6502 would have cost if they implemented all these features but:

-Everything the 65c02 already added.
-ADD and SUB without carry
-Using X and Y registers themselves as an addressing mode
-ADX/ADY/SBX/SBY ...

Even though the 6502 was supposed to be the original RISC CPU, later RISC CPUs like ARM went in a completely different direction, with less addressing modes but more registers. I always wondered what would've happened if the makers of the 6502 took the approach of more registers but less addressing ...

Is this for the 8-bit 6502 or the 16-bit 65816?

You may find this thread of interest:

http://forum.6502.org/viewtopic.php?f=2&t=6838

There is code there. One version where I implemented a 32x32 multiply using 128KB tables held in RAM was pretty fast.. But "stacking" a 16x16 to give 32x32 is relatively straightforward - this is for the case of ...

That's always been a headscratcher for me. They have "ldy abs,x" and "ldx abs,y" so you would think they would have a "sty" and "stx" to go with it but they don't, and the opcode number you would expect these instructions to be, both have illegal opcodes, instead of what you would expect.
Note ...

https://www.masswerk.at/nowgobang/2021/ ... al-opcodes

From this article it is speculated that the illegal instructions "SHY abs,x" and "SHX abs,y" were glitched versions of "STY abs,x" and "STX abs,y".

That's always been a headscratcher for me. They have "ldy abs,x" and "ldx abs,y" so you would think they would have a "sty" and "stx" to go with it but they don't, and the opcode number you would expect these instructions to be, both have illegal opcodes, instead of what you would expect.

When I'm looking at hardware specs at old school game systems from the late 80s and early 90s it makes me scratch my head wondering there wasn't a cheaper alternative to the 68000 that also had a nice instruction set. I think the 68000 instruction set can be almost made into RISC cpu if they ...

Maybe a dummy cycle reduce mode, where instructions that normally take 2 cycles take 1 cycle.

When I'm looking at hardware specs at old school game systems from the late 80s and early 90s it makes me scratch my head wondering there wasn't a cheaper alternative to the 68000 that also had a nice instruction set. I think the 68000 instruction set can be almost made into RISC cpu if they removed ...

Back in the 80s and 90s you'd think a 24-bit address is enough.

Why was having an absolute address mode missing in the majority of RISC CPUs? If you have 4 bits for the register number, 24 bits for the address, you still have 4 bits left for the instruction field, which is perfectly fine as long as it's limited to loads and stores.

One little fun fact about the SNES CPU, the speed is often quoted as 3.58Mhz, however that is the maximum speed. It also can run at 2.68Mhz, and most SNES games were released on cartridges where the cheaper ROMs only supported 2.68Mhz. Like BDD mentioned, it slows down to 1.79Mhz during port access ...