Search found 17 matches

by Karatorian
Sat Feb 11, 2012 4:34 am
Forum: Programmable Logic
Topic: Beginners CPLD
Replies: 46
Views: 8062

I'm a beginner interested in CPLDs as well and was wondering who's tools have the best Linux support. Any un*x users care to comment?
by Karatorian
Sat Apr 16, 2011 6:12 am
Forum: Hardware
Topic: Micro UK101 Build
Replies: 211
Views: 56184

Driving the UK101 odd the Speccy's power supply and clock signal is a possibility but will require some thought as I don't want to solder wires direct to the edge connector.
Well, this suggestion is definitely a hack and wouldn't be recommended for long term use, but do you have any clothespins ...
by Karatorian
Sat Apr 16, 2011 5:49 am
Forum: Hardware
Topic: My Mainboard Design
Replies: 34
Views: 7889

OE\ or W\ need to be low when Φ2 is high , not low.
Somehow I managed to get the phase of Φ2 backwards. Thanks for pointing that out. I'll have to go through the rest of the circuit and see if I've made the same mistake elsewhere.

Yes, I forgot some call Φ0 "Φ2 in". On the DIP, it's pin 37.
Yep ...
by Karatorian
Wed Apr 13, 2011 7:20 pm
Forum: Hardware
Topic: My Mainboard Design
Replies: 34
Views: 7889

I don't want to be controversial, but I'm not sure this is true. Garth has a specific point about 6522, and BDD has a general rule which he acknowledges isn't used by everyone.
So, out of curiosity, do you qualify device selection based on PHI2?

My feeling is that I've seen conversations but I ...
by Karatorian
Wed Apr 13, 2011 6:41 pm
Forum: Hardware
Topic: My Mainboard Design
Replies: 34
Views: 7889

The SRAM's OE\, CS\, and WE\ inputs are just that, meaning active low, not active high. ... You'll need to change some logic.
Thanks for pointing that out. The SRAM's /E pin (/CE) should be tied to ground, not Vcc, and likewise with the FRAM's /G (/OE) pin. I somehow got them mixed up when I was ...
by Karatorian
Tue Apr 12, 2011 5:10 am
Forum: Hardware
Topic: Micro UK101 Build
Replies: 211
Views: 56184

Not sure what the thing will do if it's in ROM and the RAM is empty (or vice versa). Will it cycle?
Well, the first thing it will do is go to the reset vector 0xEAEA. Then, if that's in the ROM area, it'll start executing NOPs until it reaches 0xFFFF. At that point, the program counter wraps ...
by Karatorian
Tue Apr 12, 2011 4:55 am
Forum: Hardware
Topic: My Mainboard Design
Replies: 34
Views: 7889

I've made some more changes to my design . I added a power connector, some pull-up resistors, clock generation, and a reset controller. I also fixed and improved the address decoding, rearranged the bus headers, and redid the whole layout using bus lines, which makes it a lot less messy.

The power ...
by Karatorian
Tue Apr 05, 2011 5:20 am
Forum: Hardware
Topic: My Mainboard Design
Replies: 34
Views: 7889

Bus Design

I think I've figured (at least part of) my question about (potentially) unused inputs on my bus. Basically, I need pull-up or pull-down resistors to set the default state of these inputs. However, I don't know exactly what size of resistors to use.

I came across an informative article Implications ...
by Karatorian
Sat Apr 02, 2011 6:35 am
Forum: Hardware
Topic: My Mainboard Design
Replies: 34
Views: 7889

I haven't been working on my mainboard design much. (I got distracted with ideas for a USB FRAM/EPROM programmer.) However, I came up with a new address decoding scheme (using a '138), which lead to a more organized (if still unpopulated) memory map.

As before, the low 32k is the SRAM. The high 32k ...
by Karatorian
Tue Mar 15, 2011 3:34 am
Forum: Hardware
Topic: My Mainboard Design
Replies: 34
Views: 7889

Sorry about the 404, I'm such a scatter brain sometimes. It's fixed now.

Unused inputs should be tied to a defined logic level. You could for example define a "logic 1" signal with a single 10kOhm to VCC and use that for all inputs. OTOH I normally connect them directly to VCC, but that has bitten ...
by Karatorian
Mon Mar 14, 2011 7:20 pm
Forum: Hardware
Topic: IO select
Replies: 5
Views: 2641

Re: IO select

kc5tja wrote:
It shouldn't -- the only difference between a 13-input and 2-input NAND gate is the number of emitters on the input transistor (assuming you're referring to TTL here).
I'm assuming he means that building a 13 input NAND using discreet components with less inputs would add gate delays.
by Karatorian
Mon Mar 14, 2011 6:55 pm
Forum: Hardware
Topic: My Mainboard Design
Replies: 34
Views: 7889

My Mainboard Design

I've always wanted to build a computer. So lately I've been working on a design for a simple 6502 based machine. As I don't have a whole lot of electronics experience, I'm trying to keep things simple for now.

I've started working on a design, which you can download here . The generic logic gates ...
by Karatorian
Mon Mar 14, 2011 6:21 pm
Forum: Hardware
Topic: Idea for an Advanced MMU for the 6502
Replies: 11
Views: 3191

Only quick: you could use a LUT and use one bit in the LUT to define if the LUT entry is valid, and if not fall back to your read-from-main-memory approach (using the LUT as cache). That is, as far as I understand, what current CPUs do.
Well, they actually use content addressable memory for the ...
by Karatorian
Mon Mar 14, 2011 10:54 am
Forum: Hardware
Topic: Idea for an Advanced MMU for the 6502
Replies: 11
Views: 3191

One of my earlier designs actually used a dedicated RAM to store the page table, however, I decided against it because of the need to reload the entire table every task switch. If one used larger page sizes, the overhead of doing so wouldn't be too bad, but 256 byte pages just feel natural on the ...
by Karatorian
Sun Mar 13, 2011 2:06 pm
Forum: Hardware
Topic: Idea for an Advanced MMU for the 6502
Replies: 11
Views: 3191

Oh, I'm aware of the 65816, but it kinda goes against the grain of this idea. Basically, the idea was to build a full-featured MMU for a processor that was never designed to have one. It's kinda a silly bit of overkill, but it's interesting from a design perspective. To be honest, the idea (to make ...