Risc v Cisc: A history lesson

The way to maximize a cpu's performance is to match the instruction cycle period to the memory cycle period.

Back in the 60's memory accesses were SLOWwwwwwww while transistor based cpu instructions were relatively fast. So everyone tried to make their instructions ...

The code coverage test is interesting. Did you run with RDY toggling ? If you can find out what wasn't tested, we could find ways to improve the test suite.

I checked on that. The only lines that were never executed involved RDY , IRQ and NMI. They were all tied off. Looks like the only ...

I did run Klaus's test on Arlets core and it passed. Here is the code coverage report
from covered. I will try to see if I can extract the untouched code.

John Eaton



Covered covered-0.7.10 -- Verilog Code Coverage Utility
Written by Trevor Williams (phase1geo@gmail.com)
Freely distributable ...

Zero-page on-chip is a remedy (albeit only a partial remedy) for the point Arlet raises. As for allowing only word-aligned access when z-pg pairs are used as pointers, that implies the least-significant bit of the z-pg address in the instruction would always be taken to be zero. Ie, the bit is ...

If so, if the 65Org16.b core runs on a Xilinx Spartan 6 FPGA at 100MHz, how fast could it run on an ASIC?


Todays processes can boast clk speeds into the multi gigihertz but that requires custom designs and significant pipeling. If you can run your clock @ 2 Ghz but if it needs a 20 deep pipeline ...

And while I'm at it you have a register named "bit" in cpu.v. This is a system verilog keyword and verilator won't accept it. Arlet's code used both bit and logic but I see that you fixed logic already

BCD mode isn't supported on Ed's. I completely removed it on mine, even the opcodes and flags.

Is there a way to bypass BCD mode in your testing?


Its not the testing thats the problem. If you `define BCD_ENABLE then you have a port that is listed twice in the instantiation but if you don't ...

Hi John,
if you go upstream and pick up my https://github.com/BigEd/verilog-6502 do you get good results? I would hope you would!
Cheers
Ed



Doesn't even compile.

You have the port BCD listed twice when you define BCD_ENABLE.



/*
* ALU
*/

ALU #(.dw(dw)) _ALU(
.clk(clk),
.op(alu_op ...

That would be:

https://github.com/ElEctric-EyE/verilog-6502

Klaus2m5 has written a functional test for the 6502 and presented it in this thread.

The other PDF's in your doc's folder from your project on opencores.org are good reading.

I've not had a chance to test your project out yet, just thought I'd say welcome ...

I would like to introduce you to a opensource project that I have been maintaining on opencores.org

It's name is socgen and it provides a set of tools and tool flows so that a designer can easily create
and verify a system-on-chip (soc) on any home pc. It uses ip-xact to hold all the design ...

you are buying a card that costs maybe a $1 to make and put on the shelf.
If you know of a way to make a card for a dollar, I'd like to know about it. I really don't think you can even make the bare board for that, regardless of volume, and that's before putting any components on it, packaging it ...

When I was provisioning engineer at CariNet, our prices for CPUs weren't substantially less than what you could purchase at other retailers.
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You not buying hardware, you are buying a card that costs maybe a $1 to make and put on the shelf. If sold then Intel picks ...

Unused circuitry still draws power that I have to pay for.

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Not any more. You isolate blocks on their own switched power island and only turn on when they are needed.

Si is now so cheap it is a commodity. Buy a coke at McD's and it only costs them about $.02 cents (less ...

This makes me frothingly livid.

Intel wants to charge $50 to unlock stuff your CPU can already do

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It looks like Intel marketing is taking things to a new level. This allows them to offer a lower entry price for their part to attract ...